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Video Transcoder Cores

System-On-Chip Technologies Inc.

Member

The Transcoder IP Core leverages SOC's low-latency Encoders and Decoders to deliver seamless, high-quality video conversion in both directions. It supports low-latency transcoding, ensuring efficient and comprehensive compatibility.

By using the transcoder cores directly, FPGA resources are saved as the Video input and Video output paths and logic resources are not required. Instead the Decoder and Encoder cores, share a common memory space to facilitate the transcoding.

Key Features

  • Low Latency
  • Optimized resources
  • Real-time transcoding
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Keyfeatures main image

Offering Brief

Offering Brief

Device Family Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Agilex™ 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Stratix® V E FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench No
Evaluation License No
Design Examples Available Yes
Demo No
Compliance No
Latest Quartus Version Supported 24.3.0
Development Language Encrypted VHDL

IP Core

Integration Guide

API Register Map

Sample Integration

Ordering Information

Documentation & Resources

Market Segment and Sub-Segments