MAC-SeC-MG

The MAC-SEC-MG IP core implements a compact and configurable custom-hardware protocol engine for the IEEE 802.1AE (MACsec) standard. It supports the AES-GCM and AES-GCM-XPN cipher suites provisioned by the MACsec standard and the VLAN-in-Clear im-provement. The engine is silicon- and performance-optimized for networks operating from 2.5 Gbps to 10 Gbps and beyond; up to 16.75 Gbps is possible with this core.

Featuring a configurable number of Security Associations (up to 64k), this protocol engine supports multiple security channels and can implement multiple Security Entities (SecYs). It operates in full-duplex mode at line speed in each direction for 2.5 Gbps to 16.75 Gbps connections. It does so by implementing a 128-bit wide data path, which provides adequate performance while minimizing silicon re-sources.

Designed for ease of integration, the MAC-SEC-MG core is a fully synchronous, single-clock domain design that uses standardized inter-faces and can be optionally pre-integrated with companion cores available from CAST.

The control and status registers of the core are accessible via a generic 32-bit memory-mapped slave interface. Interface bridges deliv-ered with the core can convert this generic host interface to a 32-bit AMBA® APB or AHB-Lite, Avalon®-MM, or Wishbone interface. Pack-et data are input and output via AXI Stream interfaces with configurable data width, enabling direct connection to Ethernet MACs, PTP timestamping units, or other higher-layer protocol engines. Interface bridges and a DMA engine capable of driving the AXI Stream inter-faces are available separately. They can be used in cases where moving data to and from the core is preferable over a memory-mapped bus. The core can be delivered pre-integrated with the Low-Latency Ethernet MAC or any Ethernet TSN cores available from CAST.