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RDMA IP Core for RoCE v2 at 10 Gbps

Grovf Inc.

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GROVF RDMA IP Core for RoCE v2 is a soft IP solution for implementing RDMA over Converged Ethernet in FPGA-based systems. It combines FPGA IP, host drivers, reference design components, and software examples to simplify integration and accelerate development.

The solution supports hardware-operated RDMA services and standard RDMA operations, including SEND, RDMA READ, and RDMA WRITE. With standard Verbs API support, dynamic configuration, hardware retransmission, and compatibility with known RNIC and soft RoCE v2 implementations, GROVF RDMA IP provides a practical path to deploying standards-based RDMA functionality on FPGA platforms.

Designed for low-latency 10GbE applications, the IP helps customers reduce software overhead, improve data movement efficiency, and integrate RDMA capability into FPGA-based networking, storage, and acceleration systems. The solution supports both Initiator and Target functionality, making it suitable for full RNIC-cl...

GROVF RDMA IP Core for RoCE v2 is a soft IP solution for implementing RDMA over Converged Ethernet in FPGA-based systems. It combines FPGA IP, host drivers, reference design components, and software examples to simplify integration and accelerate development.

The solution supports hardware-operated RDMA services and standard RDMA operations, including SEND, RDMA READ, and RDMA WRITE. With standard Verbs API support, dynamic configuration, hardware retransmission, and compatibility with known RNIC and soft RoCE v2 implementations, GROVF RDMA IP provides a practical path to deploying standards-based RDMA functionality on FPGA platforms.

Designed for low-latency 10GbE applications, the IP helps customers reduce software overhead, improve data movement efficiency, and integrate RDMA capability into FPGA-based networking, storage, and acceleration systems. The solution supports both Initiator and Target functionality, making it suitable for full RNIC-class deployments. It includes hardware-operated RC, UC, and UD services, SEND, RDMA READ, and RDMA WRITE operations, hardware retransmission, memory protection domains, configurable RDMA queue pairs, and dynamic configuration through the Verbs API.

GROVF Full RDMA is designed for demanding infrastructure use cases where high throughput, low latency, and customization are required. Customers can use it to build FPGA-based SmartNICs, HPC networking systems, GPGPU scale-out fabrics, database acceleration platforms, and storage networking solutions. Programmable congestion management, error recovery, and acknowledgement mechanisms allow system architects to tune RDMA behavior for their specific deployment requirements.

Key Features

  • Hardware support for RC, UC, and UD services
  • Supports SEND, RDMA READ, and RDMA WRITE operations
  • 10 Gb/s throughput with under 2.7 µs roundtrip latency
  • Standard Verbs API support for host-side integration
  • Hardware retransmission with configurable RDMA queue pairs

Offering Brief

Offering Brief

Device Family Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series
Offering Status Production
Integrated Testbench No
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance No
Latest Quartus Version Supported 25.3.1
Development Language Verilog

RTL

System drivers

Verbs API Support

Documentation

Sample Software and Integration

Ordering Information

Market Segment and Sub-Segments