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Octal SPI DDR PSRAM Controller

Mobiveil Inc.

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Most wearables devices typically monitor a finite set of parameters which does not demand a lot of computing power and memory size. Thus any wearable design requires low power, lower RAM density and simplified inter face with optimal performances. These design requirements make PSRAM a natural choice for wearable applications. PSRAM has the advantages that there is no need of refresh control from external sources (unlike SDRAM) and active and standby currents are very low, therefore it has been adopted in many battery-operated mobile applications such as cellular phones and recently making its way into wearables and loT applications. Mobiveil’s approach on this emerging scenario results in a PSRAM controller named “Octal SPI DDR PSRAM controller”.

This controller supports AP Memory’s Xccela open standard Bus for digital interconnect and data communications, suitable for non-volatile and volatile memories such as PSRAM. This controller ...

Most wearables devices typically monitor a finite set of parameters which does not demand a lot of computing power and memory size. Thus any wearable design requires low power, lower RAM density and simplified inter face with optimal performances. These design requirements make PSRAM a natural choice for wearable applications. PSRAM has the advantages that there is no need of refresh control from external sources (unlike SDRAM) and active and standby currents are very low, therefore it has been adopted in many battery-operated mobile applications such as cellular phones and recently making its way into wearables and loT applications. Mobiveil’s approach on this emerging scenario results in a PSRAM controller named “Octal SPI DDR PSRAM controller”.

This controller supports AP Memory’s Xccela open standard Bus for digital interconnect and data communications, suitable for non-volatile and volatile memories such as PSRAM. This controller enables smooth integration AP memory’s of Xccela PSRAM memory chips into various new-gen devices made with mobile and wearable low power SoCs’. This memory controller implementation is designed to give the user full flexibility for driving the memory control signals and timing adjustment for data sampling

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Key Features

  • Compatible with following Xccela PSRAM devices from APMemory - 8 bit data bus – DQ[7:0] support for APSxx08L-0B device, where xx stands for memory density - 16 bit data bus – DQ[15:0] support for APSxxyyN device, where yy stands for I/O config - Possible values: xx=64, 128, 256 and yy=08, 16
  • Compatible with APS3208K device from APMemory
  • Compatible with GSE6xx8DM device from GigaDevice
  • Memory mapped access to the connected PSRAM Device
  • Octal SPI Interface with DDR mode access support
  • Wrap transfer support
  • Continuous mode Burst transfer support for efficient memory access
  • Hybrid wrap burst transfer support
  • AXI4 system interface for memory access with outstanding address support. Alternatively, AHB Lite system interface for memory access
  • APB port for control registers accesses
  • Read-Prefetch feature for efficient read data through put in AHB-Lite flavour
  • Half sleep and deep power down control through simple CSR access
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Offering Brief

Offering Brief

Device Family Agilex™ 3 FPGA C-Series, Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Agilex™ 9 FPGA Direct RF-Series, Arria® 10 Bare Die, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® II GX FPGA, Arria® II GZ FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Configuration Device EPCQ-A, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® II FPGA, Cyclone® III Bare Die, Cyclone® III FPGA, Cyclone® III LS FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, HardCopy™ II ASIC Devices, HardCopy™ III ASIC Devices, MAX® 10 FPGA, MAX® II CPLD, MAX® II Z CPLD, MAX® V CPLD, Mustang Mesa, Stratix® 10 AX FPGA, Stratix® 10 Bare Die, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GT FPGA, Stratix® IV GX FPGA, Stratix® V E FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, eASIC™ N3X Devices, eASIC™ N3XS Devices, eASIC™ N5X Devices, easicopy™
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available No
Demo No
Compliance No
Latest Quartus Version Supported 23.1.1
Development Language Encrypted Verilog, Verilog

RTL Code

System Verilog/UVM based Testbench

Test cases

Protocol checkers and bus watchers

Design Guide

Verification Guide

Synthesis Guide

Ordering Information

NA

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Documentation & Resources

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