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GROVF Full RDMA 200 Gbps

Grovf Inc.

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GROVF Full RDMA 200G is a complete RoCE v2 IP solution for FPGA-based network cards, accelerators, and DPU-class systems requiring higher-throughput RDMA connectivity. It enables customers to build programmable, RDMA-capable devices that integrate with standard Linux Verbs API environments while delivering high-speed Ethernet-based data movement. The solution supports both Initiator and Target functionality, making it suitable for full RNIC-class deployments. It includes hardware-operated RC, UC, and UD services, SEND, RDMA READ, and RDMA WRITE operations, hardware retransmission, memory protection domains, configurable RDMA queue pairs, and dynamic configuration through the Verbs API. GROVF Full RDMA 200G is designed for advanced infrastructure use cases where higher bandwidth, low latency, and protocol customization are required. Customers can use it to build FPGA-based SmartNICs, HPC networks, GPGPU scale-out fabrics, database acceleration systems, and stor...

GROVF Full RDMA 200G is a complete RoCE v2 IP solution for FPGA-based network cards, accelerators, and DPU-class systems requiring higher-throughput RDMA connectivity. It enables customers to build programmable, RDMA-capable devices that integrate with standard Linux Verbs API environments while delivering high-speed Ethernet-based data movement. The solution supports both Initiator and Target functionality, making it suitable for full RNIC-class deployments. It includes hardware-operated RC, UC, and UD services, SEND, RDMA READ, and RDMA WRITE operations, hardware retransmission, memory protection domains, configurable RDMA queue pairs, and dynamic configuration through the Verbs API. GROVF Full RDMA 200G is designed for advanced infrastructure use cases where higher bandwidth, low latency, and protocol customization are required. Customers can use it to build FPGA-based SmartNICs, HPC networks, GPGPU scale-out fabrics, database acceleration systems, and storage networking platforms.

Key Features

  • Full RoCE v2 Initiator and Target implementation
  • 100 Gbps throughput
  • Standard Linux Verbs API integration
  • Configurable RDMA queue pairs, 8K or more
  • Programmable congestion management and hardware retransmission

Offering Brief

Offering Brief

Device Family Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series
Offering Status Production
Integrated Testbench No
Evaluation License Yes
Design Examples Available Yes
Demo Yes
Compliance No
Latest Quartus Version Supported 25.3.1
Development Language Verilog

RTL

System Drivers

Verbs API support

Documentation

Sample software and integration

Ordering Information

Documentation & Resources

Market Segment and Sub-Segments