This course teaches designers to write professional, synthesizable RTL code using industry-standard Verilog HDL practices. Students will master the creation of hierarchical designs, state machines with controlled encoding, and parameterizable modules suitable for FPGA implementation. Practical labs reinforce every concept through hands-on work in the Altera® Quartus® Prime design software and functional simulation using Questa®-Altera® FPGA Edition. Emphasis is placed on writing clean, efficient, synthesizable code and developing effective testbench strategies for RTL-level debugging.