High-Level Synthesis (HLS) for FPGA Acceleration

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FPGA Authority

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High-Level Synthesis (HLS) is a transformative methodology that enables hardware designers and software engineers to describe complex algorithms in C++ and automatically compile them into synthesizable RTL code, dramatically accelerating FPGA development cycles for compute-intensive applications.

This course provides comprehensive training in the Altera HLS Compiler Pro Edition and its integration with the Altera Quartus Prime design environment. Students learn HLS-specific C++ language extensions, optimization directives, memory architecture strategies, and the complete design flow from algorithmic specification to a programmed FPGA target.

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Offering Brief

Device Family	Agilex™ 3 FPGA C-Series, Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Agilex™ 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, Stratix® 10 AX FPGA, Stratix® 10 Bare Die, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® V E FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status	Production
Prerequisites	- Solid proficiency in C or C++ programming with a fundamental understanding of digital logic design
Languages	English
Target Audience	Hardware and Software Engineers, FPGA Designers, SoC Developers, Verification Engineers, System Architects, Managers
Duration	2 Days
Hands On Lab	True
OS Support	Windows,Linux

PDF of slides, lab manual and lab files where required

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