Simics Simulator for Altera SoC FPGAs

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This course teaches the uses and advantages of the Simics® Simulator for Altera® SoC FPGAs. Students will learn to install and configure the Simics simulation environment, create and run simulation targets for Altera SoC FPGA platforms, and use the Simics command line interface (CLI) and Python scripting engine to automate simulation workflows. This begins with hardware modelling concepts, software debugging with the Simics inspection tools, network and peripheral simulation, checkpoint and restore operations, and advanced topics including fault injection, coverage collection, and CI/CD integration. Students will be equipped to replace physical hardware with high-fidelity virtual platforms for embedded software development, regression testing, and system analysis.

The course introduces Hardware-in-the-Loop (HIL) testing as the complementary physical validation methodology. Students learn HIL system architecture, real time I/O fundamentals, and hands on i...

The course introduces Hardware-in-the-Loop (HIL) testing as the complementary physical validation methodology. Students learn HIL system architecture, real time I/O fundamentals, and hands on integration with industry-standard HIL platforms.

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Key Features

Offering Brief

Device Family	Agilex™ 3 FPGA C-Series, Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Agilex™ 9 FPGA Direct RF-Series, Arria® 10 Bare Die, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® II GX FPGA, Arria® II GZ FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Configuration Device EPCQ-A, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® II FPGA, Cyclone® III Bare Die, Cyclone® III FPGA, Cyclone® III LS FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, HardCopy™ II ASIC Devices, HardCopy™ III ASIC Devices, Stratix® 10 AX FPGA, Stratix® 10 Bare Die, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GT FPGA, Stratix® IV GX FPGA, Stratix® V E FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status	Production
Prerequisites	Experience with Python scripting (variables, loops, functions, modules) and familiarity with JTAG-based debugging concepts
Languages	English
Target Audience	Hardware and Software Engineers, FPGA Designers, SoC Developers, Verification Engineers, System Architects, Managers
Duration	3 Days
Hands On Lab	True
OS Support	Windows,Linux

PDF of slides, lab manual and lab files where required

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