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Embedded Software Development for Altera SoCs

FPGA Authority

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This comprehensive course provides embedded software engineers, hardware engineers, firmware developers, and system architects with an end-to-end, hands-on mastery of software development for the Hard Processor System (HPS) embedded in Altera SoC FPGA devices including the Cyclone V SoC, Arria V SoC, Arria 10 SoC, and Agilex SoC families.

The course is structured in three progressive tiers: • Foundation: Altera SoC architecture, boot flow, the ARM toolchain, the bare-metal development environment, linker scripts, ARM MMU & cache management, interrupt handling, and robust fault management. • Integration & Production: HPS peripheral drivers, HPS-FPGA bridge interfacing and custom IP integration, DMA-optimised data movement, FreeRTOS multi-task development, Zephyr RTOS, U-Boot customisation, device tree authoring, and Linux kernel driver development. • Hardware/Software Co-Design: System partitioning methodologies, FPGA fabric accelerator design usi...

This comprehensive course provides embedded software engineers, hardware engineers, firmware developers, and system architects with an end-to-end, hands-on mastery of software development for the Hard Processor System (HPS) embedded in Altera SoC FPGA devices including the Cyclone V SoC, Arria V SoC, Arria 10 SoC, and Agilex SoC families.

The course is structured in three progressive tiers: • Foundation: Altera SoC architecture, boot flow, the ARM toolchain, the bare-metal development environment, linker scripts, ARM MMU & cache management, interrupt handling, and robust fault management. • Integration & Production: HPS peripheral drivers, HPS-FPGA bridge interfacing and custom IP integration, DMA-optimised data movement, FreeRTOS multi-task development, Zephyr RTOS, U-Boot customisation, device tree authoring, and Linux kernel driver development. • Hardware/Software Co-Design: System partitioning methodologies, FPGA fabric accelerator design using RTL and HLS, advanced AXI communication fabrics and DMA, UIO/VFIO user-space drivers, oneAPI FPGA compute, multi-core AMP partitioning with OpenAMP, functional-safety considerations, and full-stack co-design validation.

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Offering Brief

Offering Brief

Device Family Agilex™ 3 FPGA C-Series, Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Agilex™ 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, MAX® 10 FPGA, Stratix® 10 AX FPGA, Stratix® 10 Bare Die, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA
Offering Status Production
Prerequisites Familiarity with embedded systems concepts and proficiency in the C programming language.
Languages English
Target Audience Hardware and Software Engineers, FPGA Designers, SoC Developers, Verification Engineers, System Architects, Managers
Duration 3 Days
Hands On Lab True
OS Support Windows,Linux

PDF of slides, lab manual and lab files where applicable

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