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MSC-CTRL Microsecond Channel high-speed controller

Computer Aided Software Technologies, Inc (dba CAST)

Member

The MSC-CTRL IP core implements a high-speed serial interface controller designed to connect a microcontroller or SoC to external power devices or sensors. It implements the Microsecond Channel (MSC) protocols derived from the Microsecond Bus (uSB) serial concept—and acts as a bus master for downstream transmission and as a bus slave for upstream transmission. The MSC-CTRL connects microcontrollers to peripheral devices via high-speed synchronous downstream and low-speed asynchronous upstream channels. It supports up to four slave devices in the MSC mode, advanced features, fragmented command frames, and higher upstream baud rates, provide robust communication in a network of dedicated sensors or devices. The controller’s communication with the host processor is facilitated by a 32-bit AMBA® APB4 subordinate interface. The MSC-CTRL features trigger signals to facilitate easy integration with an external DMA controller and a comprehensive set of interrupt sourc...

The MSC-CTRL IP core implements a high-speed serial interface controller designed to connect a microcontroller or SoC to external power devices or sensors. It implements the Microsecond Channel (MSC) protocols derived from the Microsecond Bus (uSB) serial concept—and acts as a bus master for downstream transmission and as a bus slave for upstream transmission. The MSC-CTRL connects microcontrollers to peripheral devices via high-speed synchronous downstream and low-speed asynchronous upstream channels. It supports up to four slave devices in the MSC mode, advanced features, fragmented command frames, and higher upstream baud rates, provide robust communication in a network of dedicated sensors or devices. The controller’s communication with the host processor is facilitated by a 32-bit AMBA® APB4 subordinate interface. The MSC-CTRL features trigger signals to facilitate easy integration with an external DMA controller and a comprehensive set of interrupt sources for reporting status and error information. The silicon-proven MSC-CTRL core is designed to industry best practices and has been rigorously verified. Available functional safety documents facilitate ISO 26262 ASIL B certification.

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Key Features

  • Supported Protocols - MSC standard used by Infineon, Renesas, etc. - Microsecond Bus (uSB) per SAE 2005-01-0057
  • MSC 2nd Generation - Supports up to 4 devices - Downstream channel high-speed synchronous transfer - Upstream channel low-speed asynchronous reception
  • Ease of Integration - Configured spike/glitch filter - Repetition or Triggered Downstream Transfers - LINT-clean & clean clock-domain crossing
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Offering Brief

Offering Brief

Device Family Agilex™ 3 FPGA C-Series, Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Agilex™ 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, Stratix® 10 AX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance No
Latest Quartus Version Supported 24.3.1
Development Language Encrypted Verilog, Verilog

Verilog/System Verilog, encrypted Verilog/System Verilog, or netlist

Sample integration testbench

System Verilog testbench

Sample synthesis and simulation scripts

IPxact register models

Comprehensive documention

Ordering Information

MSC-CTRL

from Direct

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Documentation & Resources

design hub icon MSC-CTRL datasheet

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ATE

Communication Tester

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RF Instrumentation

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