This course is offered as core material followed by two independent optional sessions. The core material provides the essential, device family agnostic foundation every engineer needs before working with any Altera FPGA or SoC FPGA. It covers programmable logic history, the complete Altera device portfolio, internal FPGA fabric architecture (ALMs, memory, DSP, clocking, I/O), the Quartus Prime design flow from RTL entry through synthesis, timing closure, pin planning, and device programming, plus the high speed connectivity features (transceivers, hard IP, DDR interfaces) common to mid range and high end families. The curriculum closes with simulation, on-chip debug, partial reconfiguration, and device selection methodology.
The first optional follow-on session covers SoC FPGA architecture, Hard Processor System internals, AXI bridge and peripheral integration, Linux bring-up, Agilex SoC platforms, and hardware/software co-debug. Relevant to engineers w...
This course is offered as core material followed by two independent optional sessions. The core material provides the essential, device family agnostic foundation every engineer needs before working with any Altera FPGA or SoC FPGA. It covers programmable logic history, the complete Altera device portfolio, internal FPGA fabric architecture (ALMs, memory, DSP, clocking, I/O), the Quartus Prime design flow from RTL entry through synthesis, timing closure, pin planning, and device programming, plus the high speed connectivity features (transceivers, hard IP, DDR interfaces) common to mid range and high end families. The curriculum closes with simulation, on-chip debug, partial reconfiguration, and device selection methodology.
The first optional follow-on session covers SoC FPGA architecture, Hard Processor System internals, AXI bridge and peripheral integration, Linux bring-up, Agilex SoC platforms, and hardware/software co-debug. Relevant to engineers working with Cyclone V SoC, Arria 10 SoC, Stratix 10 SoC, or any Agilex SoC FPGA. The second optional follow-on session discusses Agilex generation architectural innovations (Hyperflex, EMIB, Foveros), power architecture and estimation, device security and Secure Device Manager (SDM), board level signal integrity, PDN design, and thermal management. Relevant to engineers targeting high performance or production grade Agilex designs.