Advanced Platform Designer

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

FPGA Authority

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This advanced course elevates engineers from solid Platform Designer users to expert-level practitioners. The first day opens with a targeted review of key intermediate concepts — BFM based simulation, interconnect generation, and hierarchical design — reinforcing the foundation before moving into expert territory. From that point, the course focuses exclusively on the techniques and knowledge that distinguish expert level Platform Designer engineers from competent users.

Coverage spans advanced BFM testbench construction and simulation automation, System Console based JTAG debug and scripting, deep interconnect analysis and performance optimization, expert level hierarchical subsystem management, high speed serial IP integration (PCIe and Ethernet), DMA engine architecture, large SoC integration strategies, and complete design for reuse and IP catalog management practices.

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Key Features

Offering Brief

Device Family	Agilex™ 3 FPGA C-Series, Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Agilex™ 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, Stratix® 10 AX FPGA, Stratix® 10 Bare Die, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA
Offering Status	Production
Prerequisites	Practical experience with Platform Designer / Qsys and writing HDL at the module/component level Working knowledge of Avalon Memory Mapped and Avalon Streaming interface specifications Familiarity with Altera Quartus Prime Pro Edition flow
Languages	English
Target Audience	Engineers and architects who work primarily in software but need to design, evaluate, or collaborate on FPGA- and SoC-based systems.
Duration	2 Days
Hands On Lab	True
OS Support	Windows,Linux

PDF of slides, lab manual and lab files where applicable

Ordering Information