High Level Synthesis Advanced Optimization Techniques

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This advanced course focuses on performance critical optimization techniques for High Level Synthesis (HLS) on Altera FPGAs using the Altera HLS Compiler Pro Edition. It is designed for engineers who have completed the “HLS for FPGA Acceleration” course (or possess equivalent hands-on HLS experience) and want to push designs from functional but slow to near hand optimized RTL performance.

Rather than re-introducing HLS concepts from scratch, the course dives deeply into how the HLS compiler makes architectural decisions, how to guide those decisions explicitly, and how to optimize throughput, latency, memory bandwidth, and resource utilization on Altera FPGA fabrics. Significant emphasis is placed on understanding compiler reports, identifying and classifying performance bottlenecks, and mastering the tradeoffs involved in aggressive optimization.

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Key Features

Offering Brief

Device Family	Agilex™ 3 FPGA C-Series, Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Agilex™ 9 FPGA Direct RF-Series, Arria® 10 Bare Die, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, Stratix® 10 AX FPGA, Stratix® 10 Bare Die, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA
Offering Status	Production
Prerequisites	Experience writing, compiling, and simulating HLS components in the Altera HLS Compiler
Languages	English
Target Audience	Hardware and Software Engineers, FPGA Designers, System Architects, Managers
Duration	2 Days
Hands On Lab	True
OS Support	Windows,Linux

PDF of slides, lab manual and lab files where applicable

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