Altera SoC Linux and Software Integration

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

FPGA Authority

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This course covers the complete software stack for Altera SoC FPGA platforms, from Yocto BSP construction and U-Boot boot configuration through Linux device tree customization, platform driver development, DMA engine integration, and runtime inference pipeline orchestration. Starting from the HPS boot sequence and progressing through kernel mode driver development, zero copy DMA buffer management, and Python/ONNX Runtime integration, participants develop production grade software infrastructure that manages custom inference accelerators. The course concludes with partial reconfiguration control from Linux, OTA update implementation.

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Key Features

Offering Brief

Device Family	Agilex™ 3 FPGA C-Series, Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Agilex™ 9 FPGA Direct RF-Series, Arria® 10 Bare Die, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, Stratix® 10 AX FPGA, Stratix® 10 Bare Die, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® IV GX FPGA
Offering Status	Production
Prerequisites	FPGA accelerator design experience, solid Linux kernel module development experience, proficiency in C programming, and familiarity with ARM architecture.
Languages	English
Target Audience	Software Engineers, FPGA Designers, SoC Developers and System Architects.
Duration	2
Hands On Lab	True
OS Support	Windows,Linux

PDF of slides, lab manual and lab files where applicable

Ordering Information