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CSENT-TX CSENT Transmitter

Computer Aided Software Technologies, Inc (dba CAST)

Member

The CSENT-TX core implements a transmitter for the Single Edge Nibble Transmission (SENT) protocol. It complies with the SAE J2716 standard and supports both synchronous and asynchronous transmission modes.

Under asynchronous mode, the core autonomously, without requiring any extra action from the host system, initiates transmission, as soon as data become available in its input-data register. Under synchronous mode, transmission is triggered by either the host system via the core’s control registers, or when the core receives a valid master trigger pulse via the SENT interface.

Designed for ease of use and integration, the core reports its status using two signals, one indicating that a transmission is in progress, and a second one reporting the completion of a frame's transmission. Furthermore, the CSENT-TX provides access to its control, status, and data registers via a 32-bit APB, or an AXI4-Lite or a generic subordinate interface. Impleme...

The CSENT-TX core implements a transmitter for the Single Edge Nibble Transmission (SENT) protocol. It complies with the SAE J2716 standard and supports both synchronous and asynchronous transmission modes.

Under asynchronous mode, the core autonomously, without requiring any extra action from the host system, initiates transmission, as soon as data become available in its input-data register. Under synchronous mode, transmission is triggered by either the host system via the core’s control registers, or when the core receives a valid master trigger pulse via the SENT interface.

Designed for ease of use and integration, the core reports its status using two signals, one indicating that a transmission is in progress, and a second one reporting the completion of a frame's transmission. Furthermore, the CSENT-TX provides access to its control, status, and data registers via a 32-bit APB, or an AXI4-Lite or a generic subordinate interface. Implementation of the core is straightforward, as the core contains no latches or tri-states, is fully synchronous with a single clock domain, and includes no multicycle or false paths.

The CSENT-TX core is designed with industry best practices, has been rigorously verified and is production proven.

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Key Features

  • SENT/SAE J2716 Transmitter: - Fast & Slow Channel - Choice between 4-bit & 6-bit CRC - Short and Enhanced Messages - Asynchronous/Synchronous modes
  • Ease of Integration: - 32-bit generic, -APB or AXI4-Lite interfaces - Optional Transmit FIFO - Reset values for registers enable autonomous transmitting
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Offering Brief

Offering Brief

Device Family Agilex™ 3 FPGA C-Series, Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Agilex™ 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 LP FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, Stratix® 10 AX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® IV GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance No
Latest Quartus Version Supported 24.3.1
Development Language Encrypted Verilog, Verilog

Verilog/System Verilog, Encrypted Verilog or System Verilog or netlist

Comprehensive documentation

System Verilog testbench

Sample synthesis and simulation scripts

IPxact register models

Ordering Information

CSENT-TX

from Direct

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Documentation & Resources

design hub icon CSENT-TX datasheet

Market Segment and Sub-Segments

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Automotive (Passenger Vehicles)

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