System Level Verification & Hardware/Software Co-Simulation

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FPGA Authority

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An advanced, hands on course designed to bridge the gap between hardware, firmware, and software validation. Participants dive into a powerful co-simulation ecosystem that integrates RTL, transaction level modeling, and QEMU based emulation to replicate real world system behavior with precision. From AXI bus functional models and UVM based testbenches to HPS boot flows and Linux bring up, this course equips engineers with the methodology and tools needed to verify complex SoC interactions early and efficiently, reducing debug cycles and accelerating time to market. Designed for engineers working on high performance FPGA systems, the training emphasizes scalable verification strategies, including constrained random stimulus, coverage driven planning, formal property verification, and robust scoreboard architectures. You’ll learn to model, simulate, and analyze HPS FPGA interfaces with confidence, ensuring protocol compliance, data integrity, and system level co...

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Key Features

Offering Brief

Device Family	Agilex™ 3 FPGA C-Series, Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Agilex™ 9 FPGA Direct RF-Series, Arria® 10 Bare Die, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, HardCopy™ II ASIC Devices, HardCopy™ III ASIC Devices, MAX® 10 FPGA, Mustang Mesa, Stratix® 10 AX FPGA, Stratix® 10 Bare Die, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® IV GX FPGA
Offering Status	Production
Prerequisites	Participants should already have a solid foundation in FPGA architecture and digital logic, plus working knowledge of SystemVerilog (including interfaces and object‑oriented constructs) and basic UVM concepts.
Languages	English
Target Audience	Experienced FPGA and verification engineers, SoC designers, embedded software developers, and system architects
Duration	2 Days
Hands On Lab	True
OS Support	Windows,Linux

PDF of slides, lab manual and lab files where applicable

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