Advanced Formal Verification

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This advanced course assumes comprehensive knowledge of “Applied Formal Verification” and applies formal methods to the problems that dominate real Altera SoC designs: bus protocol and interface verification, full SoC integration, clock and reset domain crossing signoff, arithmetic datapaths, security and information flow, DSP/AI accelerator blocks, large design proof scaling, and safety critical evidence that culminates to an advanced specification to signoff. Since this course is a follow on, it does not reteach the foundational material, it opens with a compact review that recaps the essentials including SVA, assume/assume-guarantee, proof engines, counterexample triage, and equivalence checking allowing students returning after the foundational course can recalibrate quickly. The review bridge adds no new depth; everything beyond it is new and advanced content.

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Key Features

Offering Brief

Device Family	Agilex™ 3 FPGA C-Series, Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Agilex™ 9 FPGA Direct RF-Series, Arria® 10 Bare Die, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V SX FPGA, HardCopy™ II ASIC Devices, HardCopy™ III ASIC Devices, MAX® 10 FPGA, Mustang Mesa, Stratix® 10 AX FPGA, Stratix® 10 Bare Die, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® IV GX FPGA, eASIC™ N3X Devices, eASIC™ N3XS Devices, eASIC™ N5X Devices, easicopy™
Offering Status	Production
Prerequisites	Completed the “Applied Formal Verification” course proficient in writing SVA properties, running formal tools (e.g., Questa Formal), and debugging counterexamples. Solid understanding of SystemVerilog and familiarity with Quartus Prime Pro.
Languages	English
Target Audience	Senior verification engineers, formal specialists, and FPGA/SoC designers who already use formal methods and want to tackle advanced, system‑level verification problems
Duration	2 Days
Hands On Lab	False
OS Support	Windows,Linux

PDF of slides, lab manual and lab files where applicable

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