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QECIPHY - Free Open Source physical layer implementation

Riverlane

Member

QECIPHY is a physical layer implementation according to the QECi (Quantum Error Correction interface) open standard designed for FPGA-to-FPGA communication. Originally designed for quantum error correction systems, QECIPHY is a lightweight IP that exposes a simple AXI4-Stream based interface, significantly simplifying high-speed FPGA-to-FPGA communication for any application.

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Key Features

  • Simple Interface
  • Universal Compatibility
  • Programmable Line Rate
  • Programmable Clock Sources
  • Open Standard
  • Clock Recovery
  • Error Detection
  • Functionality Verified
  • Hardware Tested
  • Multi-Platform Simulation
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Offering Brief

Offering Brief

Device Family Agilex® 7 FPGA F-Series, Agilex® 9 FPGA Direct RF-Series, Stratix® 10 AX FPGA
Offering Status Production
Integrated Testbench Yes
Design Examples Available Yes
Latest Quartus Version Supported 25.3.1
OS Support Linux, Windows
Development Language Verilog

QECIPHY is a lightweight IP that exposes a simple AXI4-Stream based interface, significantly simplifying high-speed FPGA-to-FPGA communication for any application.

Ordering Information

QECIPHY

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Documentation & Resources

design hub icon QECIPHY
design hub icon Agilex 7
design hub icon DE 10

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