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XIP8103B Pseudo Random Number Generator (PRNG) IP Core, balanced version

Xiphera’s Pseudorandom Number Generator (PRNG) IP core establishes a benchmark for hardware-based security in cryptographic systems by generating high-quality pseudorandom numbers.

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XIP8103H Pseudo Random Number Generator (PRNG) IP Core, high-speed version

Xiphera’s Pseudorandom Number Generator (PRNG) IP core establishes a benchmark for hardware-based security in cryptographic systems by generating high-quality pseudorandom numbers.

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XJAnalyser Module

XJTAG’s XJAnalyser module is a powerful tool for real-time circuit visualisation and debugging.

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XJDeveloper & XJDeveloper Plus - IDE for PCB test development

XJDeveloper is an Integrated Development Environment for development and execution of circuit tests.

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XJFlash Module

XJFlash is an advanced FPGA-based module that uses JTAG for accelerated in-system programming (ISP) of flash memories.

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XJRunner

XJRunner is a production test tool for high or low volumes with power diagnostics built in.

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XpressSX AGI-FH401G PCIe Gen5 Network Processing Board

The XpressSX AGI-FH401G is a PCIe Gen5 FPGA board based on an Intel® Agilex™ 7 I-Series SoC FPGA, designed for ultra-high-speed networking and accelerated computing applications. Featuring up to 400GbE connectivity, high-bandwidth DDR4 memory, and low-latency architecture, it is optimized for SmartNIC, cybersecurity, and real-time packet processing workloads.

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xSPI-MC: xSPI, HyperBus™, and Xccela™ Serial Memory Controller

The xSPI-MC is a versatile memory controller supporting JEDEC xSPI, HyperBus™, and Xccela™ standards, as well as proprietary SPI protocols for Flash and PSRAM. It enables easy device detection, direct boot, and operation in multiple modes: Slave (AHB slave access), DMA (with internal DMA engine), Access In-Place (AIP) via AHB/AXI, and Boot-Image copy after reset. Compatible with single to 16x SPI devices, it offers flexible configuration through registers or an auto-configuration feature using a device list. Highly customizable via Verilog defines, it allows selection of DMA, auto-configuration, and device count. Delivered with a synthesizable soft-PHY, it is FPGA/ASIC ready and requires no process-specific dependencies.

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ZipAccel-C: GZIP/ZLIB/Deflate Data Compression Core

ZipAccel-C is a custom hardware implementation of a lossless data compression engine that complies with the Deflate, GZIP, and ZLIB compression standards.The core receives uncompressed input files and produces compressed files. No post-processing of the compressed files is required, as the core encapsulates the compressed data payload with the proper headers and footers. Input files can be segmented, and segments from different files can be interleaved at the core’s input.The core’s flexible architecture enables fine-tuning of its compression efficiency, throughput, and latency to match the requirements of the end application.

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Showing 928-936 of 939 Offerings