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40G Ethernet MAC and PHY FPGA IP

The 40G Ethernet MAC and PHY FPGA IP core offers IEEE 802.3ba-2010. 40 Gbps Ethernet is an industry standard and is compliant for media access control (MAC) and PHY (PCS+PMA) functions. It enables an FPGA to interface to another device over a copper or optical transceiver module.

40G FPGA SmartNIC PCIe Card NPAC-Ketch - MLE FPGA Design

The MLE 40G FPGA SmartNIC PCIe Card is a Single-Slot FHHL PCIe SmartNIC integrating an Intel Stratix 10 GX 400 FPGA, 4x SFP for 4x 10 GigE, a FPGA-attached DDR4 DRAM via SO-DIMM and with 50 Watts TDP passive cooling front-to-back. It provides 40 Gbps Source-to-Sink Data Transport, a full accelerator to fully offload the CPU, and cost-efficient, customizable and ready-to-run.

40G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

TCP/IP Full Accelerator for 40G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width pipelined all-RTL implementation for ultra-low latency.

40G UDP Offloading Engine (UDP40G-IP)

UDP Offloading Engine IP core is a pure hardware logic solution with no CPU involvement. The UDP40G-IP is ideal for high-performance data transmission or broadcasting over network. This IP product includes a reference design, helping reduce both development time and cost.

40G UDP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

UDP/IP Full Accelerator for 40G UDP/IP connections. Including UDP, IP, MAC Layer. Pipelined all-RTL implementation for ultra low Latency.

40GbE TCP Offloading Engine IP core (TOE40G-IP)

40GbE TCP Offloading Engine (TOE40G-IP) IPcore is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU is required. TOE40G-IP built by pure hardwired logic can take place of such extra CPU for TCP protocol management.

4G LTE/LTE-A CTC

Creonic’s LTE/LTE-A IP core is an advanced, customer proven implementation of the standardized 3GPP turbo code.

50G Ethernet FPGA IP

The 50G Ethernet FPGA IP core implements the 25G & 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium and the IEEE 802.3by 25Gb Ethernet draft. The IP core provides standard media access control (MAC), physical coding sublayer (PCS), and PMA functions. The PHY comprises the PCS and PMA.

50G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

MLE 50G TCP/IP is a stand-alone TCP/IP Stack Full Accelerator Subsystem allowing 50Gbps communication at full line rate and low latency. It includes TCP, IP, MAC Layer, supports 128-bit wide full duplex data width, and pipelines all-RTL implementation for high throughput and ultra low Latency.