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Device Lifecycle Management (DLM)

Build and maintain trust into every device – from day one to end of life.

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Dexcel High-Performance Radar FPGA Processing Platform

Dexcel provides high-performance FPGA platforms for radar signal processing and high-speed data acquisition applications. The solution leverages Altera FPGA devices to implement deterministic processing, high-bandwidth data movement, JESD204 RF interfaces, and precision timing architectures for mission-critical radar and RF systems.

DG 10GbE MAC core

10GbE MAC IP Core is a hardware IP core that implements the MAC layer for 10Gb Ethernet communication. It is also specifically optimized for use with Design Gateway’s TOE10G-IP and UDP10G-IP, ensuring seamless integration and maximum performance. Compared to the standard EMAC IP provided by Altera, it offers advantages in lower latency, reduced FPGA resource usage, and greater cost efficiency.

DI2CMS - I2C Bus Interface - Master/Slave

Flexible and robust interface solution that bridges microprocessors with an I2C (Inter-Integrated Circuit) bus, offering support for both SMBus (System Management Bus) and PMBus (Power Management Bus) protocols.

DI3CM-HCI controller MIPI I3C Basic v1.1.1 specifications with Host Controller Interface v1.1 specification

MIPI I3C Basic v1.1.1 specifications with Host Controller Interface v1.1 specification - Smart connectivity for mobile, IoT, and automotive innovation

DI3CS Target Device

DI3CS Target Device - MIPI® I3C Basic Specification v1.2 compliant

DISPLAY PORT IPs

Logic Fruit's Display Port Transmitter & Receiver IP Cores support multiple line rates up to 8.1 Gbps. The IP cores have been developed as per Display Port specifications DP2.0/eDP1.5.

DMESCC - Multiprotocol Enhanced Serial Communication Controller

Dual channel Multiprotocol Enhanced Serial Communication Controller, is designed for use with 8- and 16- bit microprocessors.

DPSI5 - PSI5 - IP Core Controller

PSI5 - IP Core Controller for Peripheral Sensor Interface 5 Communication