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JPEG-DX-S: Baseline and Extended JPEG Decoder

The JPEG-DX-S IP core is an area-efficient high-performance JPEG decoder supporting Baseline and Extended Sequential DCT modes of ISO/IEC 10918-1. It decodes JPEG and Motion-JPEG payloads, supporting 8- or 12-bit samples and up to four components in standard subsampling formats. Processing one sample per cycle, it can handle multiple Full-HD channels in cost-sensitive FPGAs. One of the smallest available, it requires ~76k gates in ASICs. Once configured, the core runs standalone, parsing markers and decompressing without host intervention. It reports resolution, subsampling, and depth for correct post-processing. Integration is simple via AMBA®: AXI-Stream for pixels/data and a 32-bit APB for registers. CAST offers integration services delivering complete JPEG subsystems (decoders, video interfaces, networking stacks, etc.). Designed to industry best practices, quality is proven by verification, silicon validation, and a bit-accurate software model. Scan-ready, LINT-clean, production.

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JPEG-E-S: Baseline JPEG Encoder

The JPEG-E-S IP core supports the Baseline Sequential DCT modes of ISO/IEC 10918-1, implementing a high-performance, area-efficient hardware JPEG encoder with low latency. It produces compressed JPEG images and Motion-JPEG payloads, handling 8-bit color samples and up to four components in all common subsampling formats. Processing one sample per cycle, it can compress multiple Full-HD channels even in low-cost FPGAs. Once configured, it operates standalone without host intervention. Integration is simple via AMBA®: AXI Streaming for pixels/compressed data and a 32-bit APB slave for registers. Optional AXI Streaming allows timestamps or metadata insertion. CAST offers IP Integration Services delivering complete JPEG subsystems with video interfaces, UDP/IP or Transport Stream stacks, and other IP. Designed with industry best practices, its reliability is proven through verification, production use, and a bit-accurate software model.

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JPEG-EX-F: Ultra-Fast Baseline and Extended JPEG Encoder

This JPEG compression IP core supports the Baseline and Extended Sequential DCT of ISO/IEC 10918-1 standard. It is scalable and ultra-high-performance, while handles extremely high pixel rates using significantly fewer silicon resources and less power than encoders for video compression standards such as HEVC/H,265, DSC, AVC/H.264, or JPEG200. The JPEG-EX-F encoder accepts images with up to 12-bit color samples and up to four color components, in all widely-used color subsampling formats. It can process from 2 to 32 color samples per clock cycle enabling it to compress UHD (4K/8K) video and/or very high frame video. Standalone operation, once programmed, with straightforward SoC integration (standard AMBA I/F - AXI Streaming & APB Slave). CAST’s IP Integration Services are also available for JPEG subsystems (the JPEG decoder with video interface controllers, Hardware UDPIP or Transport Stream networking stacks, or other IP cores available from CAST).

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JPEG-EX-S: Baseline and Extended JPEG Encoder

The JPEG-EX-S IP core supports Baseline and Extended Sequential DCT modes of ISO/IEC 10918-1, implementing a high-performance, area-efficient HW JPEG encoder for ASIC or FPGA with low latency. It produces compressed JPEG images and Motion-JPEG payloads, handling 8- or 12-bit samples and up to four components in all common subsampling formats. Processing one sample per cycle, it can compress multiple Full-HD channels even in low-cost FPGAs. One of the smallest encoders, it uses ~80k gates in ASICs. Once programmed, it operates standalone without host assistance. Integration is simple via AMBA®: AXI Streaming for pixels/data and 32-bit APB for registers, with optional AXI Streaming for timestamps or metadata. CAST offers IP Integration Services delivering complete JPEG subsystems with decoders, video interfaces, UDP/IP or Transport Stream stacks, or other IP. Designed to industry best practices, reliability is proven by verification, production use, and a bit-accurate software model.

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JPEG-LS-D: Lossless & Near-Lossless JPEG-LS Decoder

The JPEG-LS-D core, a highly efficient & low-power, lossless & near-lossless image decompression engine & compliant to the JPEG-LS, ISO/IEC 14495-1 standard, can decompress any JPEG-LS stream or JPEG-LS payload of image container formats. It accepts compressed streams of images with up to 16-bit per color samples & up to 4 color components, in all widely used color subsampling formats, supporting oversize image dimension parameters & resolutions higher than 64k x 64k. With standalone operation, parsing marker segments & decompressing coded data, the core reports back the image format. APP or COM marker segments are also passed to the system via a dedicated interface. Straightforard integration, standardized AMBA® I/F (compressed data & outputs pixel data, frame format information, APP or COM marker via AXI4-Stream - access to control & status registers via 32-bit APB). A wrapper that bridges the AXI-Stream interfaces to AXI4 can optionally be delivered with the core.

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JPEG-LS-E: Lossless & Near-Lossless JPEG-LS Encoder

The JPEG-LS-E core is a low-power, high-efficient image compression engine compliant with JPEG-LS (ISO/IEC 14495-1). Based on the LOCO-I algorithm, it achieves compression ratios comparable or superior to JPEG2000 in lossless mode, while requiring far less area & memory thanks to its low complexity & line-based processing. Its Near-Lossless mode enables higher compression ratios with visually lossless quality, letting users define the max pixel error. It delivers full JPEG-LS compression efficiency in a compact, easy-to-integrate hardware block. It connects through AMBA® interfaces: AXI4-Stream for image input & compressed output, & a 32-bit APB for control & status. Once configured, it can process unlimited images without host intervention, with optional metadata or timestamps inserted via a dedicated streaming port. The core’s robustness has been proven through extensive verification & silicon validation & is delivered with a full verification environment & bit-accurate SW model.

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KEIm-A5ESoM

In recent years, FPGA devices have become increasingly low-voltage and high-speed, making it extermely difficult to development boards to mount them. As a result, product development times are getting longer and development costs are increasing. Delays in product releases can also lead to significant losses. The KEIm-A5ESoM reduces the burden of development and contributes to early product release.The KEIm-A5ESoM is a System-on-Module (SoM) powered by Agilex™ 5 SoC FPGA E-Series. The SoM board is equipped with 4GByte LPDDR4 memory for HPS, dual channels of 4Gbyte LPDDR4 memory, 32GByte eMMC memory for storage, 2Gbit QSPI flash as configuration memory.By using the KEIm-A5ESoM, it is possible to use the latest FPGA devices with minimal risk and development time.

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KiviPQC-Box - Post-Quantum Key Encapsulation and Digital Signature IP Core (ML-KEM und ML-DSA)

KiviPQC-Box - Post-Quantum Key Encapsulation and Digital Signature IP Core (ML-KEM und ML-DSA)

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KiviPQC-DSA - Post-Quantum Digital Signature IP Core (ML-DSA)

KiviPQC-DSA - Post-Quantum Digital Signature IP Core (ML-DSA)

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Showing 379-387 of 666 Offerings