banner

Find Offerings

Switch to Partners

By Source
Offering Types
Region
Device Family
Market Segments
Program Level
Sort by
By Source
Offering Types
Region
Device Family
Market Segments
Program Level
Sort by

AES-CCM: Authenticated Encrypt/Decrypt Engine

The AES-CCM IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. Two architectural versions are available to suit system requirements. The Standard version (AES-CCM-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-CCM-F) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. CCM stands for Counter with CBC-MAC mode. CCM is a generic authenticate-and-encrypt block cipher mode. CBC-MAC is utilized to generate an authentication string while CTR mode is used to encrypt. The AES-CCM core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.

View Details Right arrow Right arrow
/

AES-GCM: Authenticated Encrypt/Decrypt Engine

The AES-GCM IP core implements NIST Advanced Encryption Standard (AES) in Galois Counter Mode (GCM). GCM is an authenticate-and-encrypt block cipher mode where a Galois Field (GF) multiplier/accumulator is utilized to generate an authentication tag while CTR (Counter) mode is used to encrypt. The core processes 128-bit blocks and is programmable for 128-, 192-, and 256-bit keys. Four architectural versions are available to suit system requirements. The Standard version (AES-GCM-S), more compact using a 32-bit datapath, requires 44/52/60 clocks for each data block (128/192/256-bit key, respectively). The Fast version (AES-GCM-F) achieves higher throughput using a 128-bit datapath and requires 11/13/15 clocks for each data block depending on key size. For high-throughput applications there are two additional versions. The High Throughput AES-GCM-X can process 128 bits/cycle and the Higher Throughput AES-GCM-X2 can process 256 bits/cycle respectively independent of the key size.

View Details Right arrow Right arrow
/

AES-P: Programmable Advanced Encryption Standard Engine

The AES-P encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. Two architectural versions are available to suit system requirements. The Standard version (AES-P-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-P-F) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. It can be programmed to use any of the following cipher modes: CBC, CTR, ECB, and OFB. The core works with a pre-expanded key, or with optional key expansion logic. The AES-P core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.

View Details Right arrow Right arrow
/

AES-XTS: Storage Encrypt/Decrypt Engine

The AES-XTS encryption IP core implements hardware encryption/decryption for sector-based storage data. It uses the AES block cipher, in compliance with the NIST Advanced Encryption Standard, as a subroutine. The core processes 128 bits per cycle, and is programmable for 128- and 256-bit key lengths. Two architectural versions are available to suit system size and throughput requirements. The High Throughput XTS-X is more compact and can process 128 bits/cycle independent of the key size. The Higher Throughput XTS-X2 can process 256 bits/cycle independent of the key size. Both versions have a 128-bit data path. XTS (XEX-based Tweaked Codebook Mode with Ciphertext Stealing) is a mode of AES that has been specifically designed to encrypt fixed-size data where a possible threat has access to the stored data.

View Details Right arrow Right arrow
/

Agilex 7 and Stratix 10 FPGA E-Tile Hard IP

The Agilex 7 and Stratix 10 FPGA E-Tile incorporates a configurable, hardened Ethernet protocol stack compatible with the IEEE 802.3 High-Speed Ethernet Standard and the 25G and 50G Ethernet Specification, Draft 1.6 from the 25G Ethernet Consortium. The Intellectual Property (IP) core provides access to this hard IP at data rates of 10 Gbps, 25 Gbps, and 100 Gbps.

View Details Right arrow Right arrow
Altera logo

Agilex 7 F-Tile Ethernet Hard IP

The Agilex 7 FPGA F-Tile IP core implements Ethernet at data rates of 10 Gbps, 25 Gbps, 40 Gbps, 50 Gbps, 100 Gbps, 200 Gbps and 400 Gbps. The user can choose a media access control (MAC) and a physical coding sublayer (PCS) variation, a PCS-only variation, a Flexible Ethernet (FlexE) variation, or an Optical Transport Network (OTN) variation.

View Details Right arrow Right arrow
Altera logo

Agilex 7 I-Series 041b 3UVPX Plug In Module

A 3U VPX card featuring an Agilex 7 I-Series FPGA with 4 F-tiles, designed to deliver high-performance connectivity via PCIe Gen 4 and 40G Ethernet. Optimized for defense, aerospace, and high-performance computing systems. Supports high-bandwidth applications, real-time data processing, and secure communications.

View Details Right arrow Right arrow

Agilex™ 3 Development Kit: G71D

The iG-G71D is a compact and feature-rich development kit built to evaluate Altera® Agilex™ 3 SoC FPGA solutions. It offers comprehensive connectivity with 2.5G and Gigabit Ethernet, USB 3.0/2.0 via Type-C, PCIe Gen3 x4, and high-speed expansion through FMC+ and PMOD connectors. With additional interfaces including JTAG and a 20-pin HPS header (I2C, SPI, GPIOs), the G71D kit is ideal for prototyping embedded systems, industrial networking, and low-power edge applications.

View Details Right arrow Right arrow
/

Agilex™ 3 FPGA and SoC C-Series Development Kit

Agilex™ 3 FPGA and SoC C-Series Development Kit is a compact, power-efficient platform for embedded and edge applications, featuring DisplayPort 1.4, dual MIPI interfaces, and Raspberry Pi HAT expansion.

View Details Right arrow Right arrow
Altera logo
Listing 9 out of 566 Offerings