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Achilles Arria® 10 SoC SoM

This module is based on an altera® Arria® 10 SoC FPGA, combining FPGA performance with embedded ARM processing for flexible and compact system designs. It integrates DDR4 memory with ECC and supports multiple high-speed interfaces, enabling the development of scalable, high-performance embedded applications.

Adjustable Clock

Full standalone hardware only solution of an adjustable Counter Clock

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Advanced FPGA Design Methodologies and Techniques

This comprehensive course consolidates the full breadth of advanced FPGA design knowledge into a single intensive program.

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Advanced Verilog Design Techniques

This course teaches designers to write professional, synthesizable RTL code using industry-standard Verilog HDL practices.

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Advanced VHDL

This advanced, hands-on course is designed for experienced FPGA engineers who want to deepen their mastery of VHDL.

AES - Advanced Encryption Standard Engine

The AES encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. Two architectural versions are available to suit system requirements. The Standard version (AES-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-F) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. Various cipher modes can be supported (CBC, CFB, CTR, ECB, LRW, and OFB). The core works with a pre-expanded key, or with optional key expansion logic. The AES core is a fully synchronous design and has been evaluated in a variety of technologies. It is available optimized for ASICs or FPGAs, with complete deliverables.

AES 128 IP

AES-128 IP supports ECB mode for both encryption and decryption, processing 128-bit data blocks in a constant 11 clock cycles. It delivers 11.6 Mbps per MHz, achieving up to 4.65 Gbps at 400 MHz. Designed to enhance the security of data storage and networking IP cores, it enables secure, efficient, and high-performance applications.

AES 256 GCM 100G IP for Networking Applications

AES256-GCM-100G IP Core (AES256GCM100GIP) implements the advanced encryption standard (AES) with 256-bit key in Galois/Counter Mode (GCM) which is widely used for Authenticated Encryption with Associated Data (AEAD) application, including IPSEC, MACSEC and TLS (Transport Layer Security) versions 1.2 and 1.3. Additionally, AES-GCM is used in fiber channel communications and storage applications.

AES 256 GCM 10G25G IP for Networking Applications

AES256-GCM-10G25G IP core implements the advanced encryption standard (AES) with 256-bit key in Galois/Counter Mode (GCM) which is widely used for Authenticated Encryption with Associated Data (AEAD) application. This IP core can achieve high throughput 38.4 Gbps @300MHz, suitable to work together with our TOE10G and TOE25G IP core for high performance and secure communication applications.