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AES 256 IP

AES-256 IP supports ECB mode for both encryption and decryption, processing 128-bit data blocks in a constant 15 clock cycles. It delivers 8.53 Mbps per MHz, achieving up to 3.41 Gbps at 400 MHz. Designed to enhance the security of data storage and networking IP cores, it enables secure, efficient, and high-performance applications.

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AES 256 XTS IP

AES256-XTS IP Core implements the advanced encryption standard (AES) with XEX Tweakable Block Cipher with Ciphertext Stealing (XTS) which is widely used in protecting the confidentiality of data on storage devices.

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AES 256 XTS STG 2X IP for NVMe Gen4

AES256-XTS-STG-2X IP implements the advanced encryption standard (AES) with XEX (XOR Encrypt XOR) tweakable block cipher which operates sequences of complete blocks and is suitable for protecting the confidentiality of data on NVMe™ Gen4 storage devices.

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AES 256 XTS STG 4X IP for NVMe Gen5

AES256-XTS-STG-4X IP implements the advanced encryption standard (AES) with XEX (XOR Encrypt XOR) tweakable block cipher which operates sequences of complete blocks and is suitable for protecting the confidentiality of data on NVMe™ Gen5 storage devices.

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AES 256 XTS STG IP for NVMe Gen3

AES256-XTS-STG IP implements the advanced encryption standard (AES) with XEX (XOR Encrypt XOR) tweakable block cipher which operates sequences of complete blocks and is widely used in protecting the confidentiality of data on various storage devices with interfaces such as NVMe™ and SATA.

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AES-CCM: Authenticated Encrypt/Decrypt Engine

The AES-CCM IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. Two architectural versions are available to suit system requirements. The Standard version (AES-CCM-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-CCM-F) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. CCM stands for Counter with CBC-MAC mode. CCM is a generic authenticate-and-encrypt block cipher mode. CBC-MAC is utilized to generate an authentication string while CTR mode is used to encrypt. The AES-CCM core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.

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AES-GCM: Authenticated Encrypt/Decrypt Engine

The AES-GCM IP core implements NIST Advanced Encryption Standard (AES) in Galois Counter Mode (GCM). GCM is an authenticate-and-encrypt block cipher mode where a Galois Field (GF) multiplier/accumulator is utilized to generate an authentication tag while CTR (Counter) mode is used to encrypt. The core processes 128-bit blocks and is programmable for 128-, 192-, and 256-bit keys. Four architectural versions are available to suit system requirements. The Standard version (AES-GCM-S), more compact using a 32-bit datapath, requires 44/52/60 clocks for each data block (128/192/256-bit key, respectively). The Fast version (AES-GCM-F) achieves higher throughput using a 128-bit datapath and requires 11/13/15 clocks for each data block depending on key size. For high-throughput applications there are two additional versions. The High Throughput AES-GCM-X can process 128 bits/cycle and the Higher Throughput AES-GCM-X2 can process 256 bits/cycle respectively independent of the key size.

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AES-P: Programmable Advanced Encryption Standard Engine

The AES-P encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. Two architectural versions are available to suit system requirements. The Standard version (AES-P-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-P-F) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. It can be programmed to use any of the following cipher modes: CBC, CTR, ECB, and OFB. The core works with a pre-expanded key, or with optional key expansion logic. The AES-P core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.

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AES-XTS: Storage Encrypt/Decrypt Engine

The AES-XTS encryption IP core implements hardware encryption/decryption for sector-based storage data. It uses the AES block cipher, in compliance with the NIST Advanced Encryption Standard, as a subroutine. The core processes 128 bits per cycle, and is programmable for 128- and 256-bit key lengths. Two architectural versions are available to suit system size and throughput requirements. The High Throughput XTS-X is more compact and can process 128 bits/cycle independent of the key size. The Higher Throughput XTS-X2 can process 256 bits/cycle independent of the key size. Both versions have a 128-bit data path. XTS (XEX-based Tweaked Codebook Mode with Ciphertext Stealing) is a mode of AES that has been specifically designed to encrypt fixed-size data where a possible threat has access to the stored data.

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Showing 55-63 of 878 Offerings