Current: xSPI Initiator core.
xSPI Memory Controller Core for PSRAM, NOR Flash, STT-MRAM. Protocols: (a) JEDEC xSPI Profile 1.0, 2.0; (b) HyperBus 1.0, 2.0, 3.0; (c) OctaBus; (d) Octal Bus; (e) Exccela Bus. SLL support x8 and x16 PSRAM devices, and support chaining two x16 PSRAM devices to create x32 PSRAM channel.