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CTAccel Image Processing (CIP) Accelerator

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Current: xSPI Initiator core.  

xSPI Memory Controller Core for PSRAM, NOR Flash, STT-MRAM. Protocols: (a) JEDEC xSPI Profile 1.0, 2.0; (b) HyperBus 1.0, 2.0, 3.0; (c) OctaBus; (d) Octal Bus; (e) Exccela Bus. SLL support x8 and x16 PSRAM devices, and support chaining two x16 PSRAM devices to create x32 PSRAM channel.

CXL 3 CONTROLLER IP

The CXL 3 Controller IP is forward compatible with CXL 3.x and backward compatible with previous versions, offering flexible configurations needed for advanced systems. It supports multiple channels and configurable CXL degraded modes, ensuring seamless integration with CXL devices and enabling high-performance data transfer. Ideal for versatile system designs, it accommodates all three CXL device types to facilitate efficient connectivity and scalable architecture.

Cyclone® 10 GX FPGA Development Kit

The Cyclone® 10 GX Development Kit is a cost-effective platform for transceiver-based applications, featuring high-speed I/O and robust memory support.

Cyclone® 10 LP FPGA Development Kit

The Cyclone® 10 LP Evaluation Kit is a low-cost, low-power platform ideal for entry-level FPGA development and education.

Cyclone® V E FPGA Development Kit

The Cyclone® V E FPGA Development Kit offers a comprehensive general purpose development platform for Cyclone V FPGAs, and features an abundance of interactive options.

Cyclone® V GT FPGA Development Kit

The Cyclone® V GT FPGA Development Kit provides a robust platform for evaluating high-speed transceiver capabilities of the Cyclone V GT FPGA, featuring PCIe Gen2 x4 and DDR3 support.

Cyclone® V SX SoC Development Kit

The Cyclone® V SX SoC Development Kit offers a complete SoC FPGA platform with integrated ARM Cortex-A9 processors, ideal for embedded system development and hardware/software co-design.

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Data Management & CI/CD for FPGA

As an ICT service provider for the high-tech electronics design flow we offer data management solutions for developing firmware, and making sure that the code is complete and secured. We have developed solutions where the firmware is automatically built using makefiles using a clean build and several quality checks are performed on the completeness of the code.