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LDPC for Flash Controller (Silicon Proven IP for Altera Devices)

Mobiveil’s LDPC Controller offers advanced LDPC error correction with statistical DSP. It addresses the reliability demands of MLC, TLC, and 3D NAND at advanced geometries while significantly extending flash memory life. Optimized for ultra-low power to high-performance SSD applications, it is scalable, patented, and highly customizable.

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LDPC IP

The Low-Density Parity-Check (LDPC) IP Core is a high-throughput, low-latency forward error correction (FEC) engine designed to meet the rigorous requirements of next-generation communication and data storage systems. LDPC codes are known for their near-Shannon limit performance and are widely adopted in standards such as 5G NR, Wi-Fi 6/7, DVB-S2/S2X, G.hn, 10GBASE-T Ethernet, SATA, NVMe, and more.

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Leveraging AI Agents for SoC Design

This course equips experienced engineers and architects with the knowledge and hands-on skills needed to integrate AI agents into modern System-on-Chip (SoC) design workflows.

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Leveraging AI Agents for SoC Verification

This course prepares system architects, hardware engineers, and software engineers to apply AI agents and large language model (LLM) technology directly within their System-on-Chip (SoC) verification flows.

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LIN Bus Controller

LIN with UART half-duplex enhanced functionality - available in two versions – Basic and Safety-Enhanced

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LIN: LIN Bus Master/Slave Controller

The LIN-CTRL core is a controller that transmits and receives complete LIN frames to perform serial communication according to the LIN Protocol Specification. It can be configured before the synthesis to operate as a master, slave or include both profiles. When configured with both – master and slave, then at run-time, the LIN-CTRL can operate either as a master or as a slave and supports versions 1.3, 2.0, 2.1, and 2.2 of the LIN protocol. The message transfers can be controlled via a microcontroller interface and a LIN transceiver is needed for the connection to the LIN bus. The LIN-CTRL core is a microcode-free design developed for reuse in ASIC and FPGA implementations. The robustly verified core has been production-proven multiple times. The LIN controller core is available in two versions: Standard, and Safety-Enhanced. The Safety-Enhanced versions are certified as ISO-26262 ASIL-D Ready.

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Lithe Layer 2 IP

Pantherun’s Layer 2 Switch IP is a high-performance, FPGA-optimized solution that delivers line-rate Gigabit to 10/100Gbps switching with ultra-low latency, secure AES encryption, and field-configurable flexibility for industrial, automotive, and mission-critical networks.

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Lossless and Lossy CCSDS 122.0-B-1 Encoder

CCSDS-122-E

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Lossless and Lossy JPEG 2000 Encoder

JPEG2K-E

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Showing 568-576 of 939 Offerings