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UHS OPI PSRAM Controller (Silicon Proven IP for Altera Devices)

Targeted at wearables and low-power devices, Mobiveil’s UHS OPI PSRAM Controller supports AP Memory’s UHS series running up to 1066 MHz. It delivers low-power, high-frequency performance for memory subsystems with simplified interface requirements. The flexible architecture ensures precise control signal timing for seamless SoC integration.

Ultra-high-throughput WiFi LDPC Decoder

XCEL ASICs’ Ultra-High-Throughput Wi-Fi LDPC Decoder IP is an IEEE 802.11n/ac/ax/be–compliant (Wi-Fi 4/5/6/7) forward error correction (FEC) solution optimized for current and next-generation Wi-Fi transceivers and SoC designs. In addition to supporting earlier Wi-Fi generations, the IP enables Wi-Fi 7 (IEEE 802.11be) data rates exceeding 30 Gbps while delivering exceptional throughput-per-area efficiency, enabling very high decoding performance within a minimal silicon footprint. This combination of scalable throughput and area efficiency makes the IP particularly well suited for cost- and power-constrained, high-performance Wi-Fi transceiver chip implementations.

Universal Net Red (UNR) Complete Network redundancy solution as combination of our IP cores

All in one Network Redundancy solution

Universal Time Sync (UTS) Complete Synchronization solution as combination of our IP cores

All in one Synchronization solution

USB 10Gbps Device Controller (USB32SF)

10Gbps Device IP Core

USB 2.0 Device with FIFO Interface (USB20HF)

USB20HF IP Core

USB 2.0 Device, Software based enumeration RAM Interface (USB20SR)

USB20SR IP Core

USB 2.0 Device, Software Enumeration FIFO Interface (USB20SF)

USB20SF IP Core

USB 2.0 Host Controller

USB20HC IP Core