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MPEG2 Video Decoder

Fabric only, MPEG2 Decoder IP core HD60 Decoding supporting interlaced and progressive.

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MPEG2 Video Encoder

Legacy MPEG2 Video Encoder IP core Supporting HD Progressive and Interlaced formats Runtime API

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MSC-CTRL Microsecond Channel high-speed controller

The MSC-CTRL IP core implements a high-speed serial interface controller designed to connect an SoC to external power devices or sensors. It implements the Microsecond Channel (MSC) protocol and acts as a bus master for downstream and as a bus slave for upstream transfers. The MSC-CTRL is integrated to peripherals via high-speed synchronous downstream and low-speed asynchronous upstream channels. It supports up to four slave devices in the MSC mode, advanced features, fragmented command frames, and higher upstream baud rates, provide robust communication in a network of dedicated sensors or devices. The IP includes a 32-bit AMBA® APB4 subordinate interface and includes trigger signals to facilitate easy integration with an external DMA controller. The silicon-proven MSC-CTRL core is designed to industry best practices and has been rigorously verified. Optional functional safety documents facilitate ISO 26262 ASIL B standard.

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Multi User NVMe IP core for Gen4 (muNVMe-IP)

muNVMe-IP (Multi-user NVMe IP) is designed and optimized for simultaneous access to a single NVMe™ SSD by multiple data streams. It delivers near-maximum SSD throughput for both mixed and same-direction read/write operations. Ideal for applications requiring high performance and multiple data streams or sequential access via pure hardware logic without CPU or OS.

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Multi-point Input / Output Expander, Altera Cyclone® FPGA Design

Multi-point Input / Output Expander, Altera Cyclone® FPGA Design

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Multi-Rate Ethernet PHY FPGA IP

The Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates from 10M to 10GbE in accordance with the IEEE 802.3 Ethernet Standard without any design regeneration or device reconfiguration.

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Multichannel DMA IP for PCI Express

Accelerate designs with Multichannel DMA for PCIe IP – fast and efficient data movement, flexible features, and Linux driver support.

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MyMENSCH™ - W65Cx65MMC10M08 Development Board

SBC/Development board based on MAX10M08SA

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N-EMB-100 ZEKE EtherCAT Master_Slave

The N-EMB-100 platformThe N-EMB-100 is a high-performance industrial device platform equipped with an Cyclone® V SoC. It has two Arm Cortex-A9 processor cores and can use Linux, etc. in SMP mode. It has four RJ45 connectors: two ports for Arm-side Gigabit Ethernet and two ports for FPGA-side EtherCAT. Since it is equipped with two 10/100 PHYs on the FPGA side, it can also use Altera's TSE MAC IP, etc. QSPI or microSD cards can be used as boot memory, and the boot source can be selected with jumpers on the board. This board can be used in a variety of EtherCAT (hardware master/software master and slave) applications.Hardware Master: You can evaluate our hardware master using the Ethernet on the FPGA side.Software Master: You can implement various paid software masters using the Ethernet on the Arm side. We can also provide a demo environment with an open-source master stack implemented.Slave: It can also be used as a slave by implementing an EtherCAT slave IP, such as one made by BECKH

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Showing 604-612 of 898 Offerings