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PROFIBUS Master Subsystem for Altera FPGA

The PROFIBUS DP Master Subsystem for Alter FPGAs integrates all components required for implementing a complete PROFIBUS DP Class1 and Class2 Master based on FPGA technology. Thus, no specific fieldbus controller ASIC is needed in addition.

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PROFIBUS Slave Subsystem for Altera FPGA

PROFIBUS Slave for Altera FPGA provides an optimized PROFIBUS DP IP Core and a Communication Processor for the Integration of PROFIBUS DP and other industrial networks into field devices. It uses the same API for all supported protocols.

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PROFINET Controller Subsystem for Altera FPGA

PROFINET Controller for Altera FPGA provides controller connectivity for PLC, PAC, DCS and similar systems. It comprises an industrial switch IP core and all required protocol software already running on a softcore processor. It is an encapsulated PROFINET communication subsystem simply downloadable into an FPGA.

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PROFINET Device Subsystem for Altera FPGA

PROFINET Device for Altera FPGA provides an optimized Switch IP Core and a Communication Processor for the Integration of PROFINET and other industrial networks into field devices. It uses the same API for all supported protocols.

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PSI5-HOST Peripheral Sensor Interface (PSI5) Host Controller

The PSI5-HOST IP core is a configurable automotive Peripheral Sensor Interface (PSI5) host controller implementing the ECU side of PSI5 communication systems, supporting PSI5 Specification v2.3 with backward compatibility to PSI5 v1.3. It enables robust communication between ECUs and automotive sensors using a low-cost two-wire interface over sensor power lines. The core supports synchronous and asynchronous modes, ECU-to-sensor downstream communication via tooth-gap or pulse-width encoding, and sensor-to-ECU Manchester-coded upstream messaging. Safety-oriented features include programmable watchdog timing slot monitoring, receive frame timestamps, and CRC or parity-based data protection per the PSI5 specification, enabling integration into ISO 26262-oriented systems. Register access is performed via an AMBA APB interface. The silicon-proven core is rigorously verified, with optional functional safety documents and diagnostic features aiding ISO 26262 integration.

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PSS Servo

The PSS Servo is a software application operating in the Linux user space, implementing a high-performance servo capable of handling noisy networks and supporting a wide range of PLLs and oscillators.

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PTP Hybrid Clock (IEEE1588 – Precision Time Protocol)

Full standalone hardware only solution of a PTP Hybrid Clock (Combined PTP TC and OC)

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PTP Ordinary Clock (IEEE1588 – Precision Time Protocol)

Full standalone hardware only solution of a PTP Ordinary Clock

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PTP Timestamp Unit (IEEE1588 – Precision Time Protocol)

PTP Timestamp Unit

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Showing 712-720 of 939 Offerings