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SystemC training

For the shift-left in development, you want to simulate your design early in the development phase. SystemC is used widely by the industry to model your design blocks, and is supported by various simulators. Want to learn how to use this? Dizain-Sync can teach you!

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SystemVerilog for Design

This course is aimed at RTL designers who wish to learn about the features of SystemVerilog for RTL design.

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SystemVerilog for Verification

This course introduces engineers to developing comprehensive verification environments using SystemVerilog.

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SystemVerilog for Verification

This 5-days course designed for ASIC & FPGA verification engineers that would like to use the SystemVerilog and UVM to verify digital designs. SystemVerilog is a significant new enhancement to Verilog and includes major extensions into abstract design, test-bench, formal, and C-based APIs.

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tCAM IP

tCAM-IP is a high-performance, ultra-low-latency, and configurable Ternary Content-Addressable Memory IP, delivering deterministic search at 300 MSPS with a fixed latency of 7 clock cycles. It enables packet matching and filtering at up to 300 million packets per second over 40G/100G Ethernet. Ideal for applications such as packet filtering, intelligent switches/routers, deep packet inspection, and network security.

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TCC IP

Turbo Convolutional Codes (TCC) are an advanced class of Forward Error Correction (FEC) techniques that provide near-Shannon limit performance in digital communications. Widely adopted in 3G, 4G LTE, satellite, aerospace, and defense-grade communication systems, TCCs significantly enhance data integrity and transmission reliability in noisy environments.

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TCP/IP Offload Engine

Chevin Technology’s TCP/IP Offload Engine is a high‑performance, all‑RTL Ethernet stack that enables reliable, low‑latency network communication by offloading TCP/IP processing entirely into FPGA logic. It reduces CPU load, increases throughput, and simplifies integration, providing a scalable and efficient solution for network‑enabled applications

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TCPIP-100G: 100G TCP/UDP/IP Hardware Stack

The TCPIP-1G/10G core is a complete hardware TCP/IP stack that supports up to 32k sessions, DHCP, UDP with multicast, and offers configurable low-latency cut-through or reliable store-and-forward modes.

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TCPIP-1G/10G: 1G/10G TCP/IP Hardware Stack

The TCPIP-1G/10G core is a complete TCP/IP hardware protocol stack, enabling systems to connect to IP networks and exchange TCP data without a host processor. Acting as server or client, it autonomously opens, maintains, and closes TCP connections. Network parameters are configured via control registers, while data is exchanged over streaming interfaces. The core is highly configurable: up to 32,768 simultaneous TCP sessions can be supported, or just one for minimal area designs. Options include a DHCP client, reassembly of out-of-order packets, and integration of a UDP hardware stack with IGMPv3 multicast. Users may select cut-through mode for ultra-low latency and minimal buffering, or store-and-forward mode for verified, in-order delivery. Available in RTL or FPGA netlist form, the core is rigorously verified and provided with testbench, synthesis/simulation scripts, and full documentation, making it ideal for applications ranging from servers to edge devices.

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Showing 784-792 of 898 Offerings