banner

Find Offerings

Switch to Partners

By Source
Offering Types
Region
Device Family
Market Segments
Program Level
Sort by

Loading

By Source
Offering Types
Region
Device Family
Market Segments
Program Level
Sort by

Terasic Cyclone® V SoC Development Kit with HSMC Connector (DE10-Standard)

The DE10-Standard Development Kit features an Altera SoC FPGA with dual-core ARM Cortex-A9 processors and programmable logic, delivering high performance, low power, and flexible reconfigurability for diverse design needs.

View Details Right arrow Right arrow
/

Terasic SoC System on Module Evaluation Kit

The Terasic SoC System on Module Evaluation Kit consists of the TSoM module and a TSoM-based board. The TSoM is a pocket-sized module powered by the latest Intel® Cyclone® V SoC FPGA. The board leverages the ARM dual-core Cortex-A9 CPU and 110K FPGA logic elements to deliver the lowest system cost and optimal power efficiency. The TSoM-based board expands the TSoM module with a variety of practical interfaces, enhancing overall equipment effectiveness (OEE) through IoT data and AI applications.

View Details Right arrow Right arrow
/

ThunderFjord Agilex™ 7 M-series FPGA SmartNIC

Silicom ThunderFjord board is high-performance programmable PCIe Gen5 x16 server adapter based on Agilex™ M-series FPGA (AGMF039 or AGMF032 option).Interfaces: Dual QSFPDD56 (2×400GE), supports multiple link combinations.Memory: Up to 32GB HBM2e with 2×2.6 Tbps bandwidth.Expansion: 2×ARC6-16 connectors (16×28Gbps) for PCIe, Ethernet, or interconnect options.Features: CXL 1.1/2.0, Quad-core ARM Cortex A53, flexible connectivity with breakout and flyover cables, direct card-to-card links.Applications: AI, machine learning, analytics, and other performance-intensive workloads.

View Details Right arrow Right arrow
/

Titan S10 SOM

The Titan S10 SOM is a compact, high-performance FPGA module based on the Altera Stratix® 10 SoC with 1.1M logic elements, dual DDR4 memory, high-speed transceivers, and flexible FMC/FMC+ interface options for compute-intensive embedded applications.

View Details Right arrow Right arrow
/

TLS 1.3 Client 10Gbps IP core (TLS10GC-IP)

TLS1.3 IP (Transport Layer Security IP) is a CPU-less, high-performance TLS v1.3 protocol engine for FPGA acceleration, requiring no CPU or external memory. It enables maximum Gigabit Ethernet throughput for secure data transmission over 1G/10G/25G/100G networks, making it ideal for Industrial IoT, automation, aerospace, and defense applications. Our demo showcases high-throughput HTTPS upload/download with a standard web server, achieved through pure hardware logic on FPGA.

View Details Right arrow Right arrow
/

TLS 1.3 Server 10Gbps IP core (TLS10GS-IP)

TLS1.3 IP (Transport Layer Security IP) is a CPU-less, high-performance TLS v1.3 protocol engine for FPGA acceleration, requiring no CPU or external memory. It enables maximum Gigabit Ethernet throughput for secure data transmission over 1G/10G/25G/100G networks, making it ideal for Industrial IoT, automation, aerospace, and defense applications. Our demo showcases high-throughput HTTPS upload/download with a standard web server, achieved through pure hardware logic on FPGA.

View Details Right arrow Right arrow
/

TOD Master (Time of Day, NMEA)

Full standalone hardware solution of a TOD Master

View Details Right arrow Right arrow
/

TOD Slave ( Time of Day, NMEA, UBX, TSIP, ESIP)

Full standalone hardware only solution of a TOD Slave

View Details Right arrow Right arrow
/

Tone Mapping Operator FPGA IP

The Tone Mapping Operator (TMO) FPGA IP corrects poorly exposed images and video to reveal invisible details.

View Details Right arrow Right arrow
Altera logo
Showing 793-801 of 898 Offerings