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TPC IP

Turbo Product Codes (TPC) are powerful Forward Error Correction (FEC) schemes that offer strong error-correcting capability with moderate complexity. TPCs are widely adopted in satellite communications, deep-space telemetry, aerospace systems, and military-grade networks, where low bit-error rates (BER) and high data integrity are essential under challenging noise conditions.

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TR10a-HL Arria® 10 FPGA Development Kit

Terasic TR10a-HL Development Kit provides the ideal hardware solution for designs that demand high capacity and bandwidth memory interfacing, ultra-low latency communication, and power efficiency. With a full-height, 1/2-length form-factor package, the TR10a-HL is designed for the most demanding high-end applications, empowered with the top-of-the-line Altera Arria 10 GX, delivering the best system-level integration and flexibility in the industry.

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TR10a-HL2 Arria® 10 FPGA Development Kit

Terasic’s TR10a-HL2 is designed to advance the agility, flexibility and speed and delivers blazing performance in cloud and data center applications.

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Training Partner

Gaining knowledge and skills is crucial in the world of electronics development to stay competitive in today’s fast growing world of technology. Do you wish to enhance your design skills so you can complete your projects faster? Sign up for one of our training in the field of electronics development tooling and design methodology.Altera FPGA training: - Introduction to VHDL. - Advanced VHDL Design Techniques. -Quartus® Prime Design Software: Foundation. - Introduction to the Platform Designer System Integration Tool (Qsys). - Designing with Nios® II Processor. -Quartus® Prime Software: Timing Analysis with Timing Analyzer. - Designing with an ARM-based SoC.Go to the website of Transfer DSW B.V and make a selection from the list of available trainings dates.

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Transparent Compression

Eideticom’s NoLoad Transparent Compression delivers high-performance inline data compression. Its NVMe-compliant interface ensures native driver support across all CPU platforms and operating systems, including Linux, FreeBSD, and Windows.

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Triple-Speed Ethernet FPGA IP

A complete 10/100/1000 Mbps Ethernet IP with flexible IP options including MAC only, PCS only, MAC + PCS, MAC + PCS + PMA, PCS + PMA.

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TSN End-Node (IEEE802.1 Time Sensitive Networking End-Node)

Full standalone hardware only solution of a TSN End-Node

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TSN Network Node (IEEE802.1 Time Sensitive Networking Switched End-Node)

Full hardware only solution for a TSN Switched End-Node

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TSN-EP-10G: 10G TSN Ethernet Endpoint Controller

The TSN-EP-10G is a highly configurable TSN Ethernet Endpoint Controller IP core designed to streamline the implementation of Time-Sensitive Networking endpoints. It provides hardware support for 802.1AS-2020, 802.1Qav, 802.1Qbv, optional 802.1Qci and 802.1Qcc. It includes a low-latency Ethernet MAC with XGMII PHY interface and AXI-Stream Host interface. The core delivers precise, deterministic latencies with minimal host software required and provides real-time timing information along with dynamic traffic-shaping adjustments. Designed for simple integration, TSN-EP-10G uses standard AMBA® interfaces: a 32-bit APB for CSR and a 128-bit AXI-Streaming interface for data packets. Optional DMA is also available. Delivered as synthesizable RTL or FPGA netlist, it includes testbenches, sample scripts, documentation and a lightweight gPTP for FreeRTOS and Linux. Suitable for automotive, industrial, aerospace, and other applications requiring low-latency, deterministic TSN communication.

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