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ALSE Advanced Logic Synthesis for Electronics

About ALSE Advanced Logic Synthesis for Electronics

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Certified Engineers

5

Languages

English, French

Advanced Logic Synthesis for Electronics (“A.L.S.E”), created in 1993, offers a complete range of IPs, Design Services, Trainings, and Boards to help you with the design of FPGA-based applications or Embedded Systems. ALSE has been partnering with Altera since more than 25 years, and we have trained thousands of engineers into designing and using Altera FPGAs. It's no surprise that we now have a very long list of IPs, aligned with the latest and most powerful FPGAs. We're are proudly exhibiting a 100% success rate on our Projects, Services and IPs, so don't be surprised if we are cautious before selling an IP. Your success matters !

Headquarters: 46 Quai Nicolas Rolin, Dijon, 21000, France

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Offering Type

offering type links Acceleration / AI / Cloud
offering type links Boards / SOMs / Dev Kits
offering type links Design Services
offering type links Education / Training
offering type links Intellectual Property (IP)
offering type links Software / OS / RTOS

Offerings

10G Ethernet processor-less stack

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Very compact and very low latency JPEG/MPEG encoder ideal for video and still pictures. Output is fully standard and decoded by all viewers.

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This compact, extremely efficient and low latency IP core is capable of decoding in real-time video on-the-fly using standard and ubiquitous JPEG compression, even on low-cost FPGAs. This IP does not require any processor nor any external memory.

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Very low latency Video Encoder supporting high resolutions and frame rates. Compression factor dynamically adjustable. Standard output format. An option allows the standard video stream to be decoded efficiently by GPU (multiple threads).

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Connect your FPGA to Ethernet without any processor and 100% efficiency !

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Complete Certified MILAN IP in an SoC-FPGA.

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The ALSE Aurora 8B/10B IP Core makes this open protocol available to all Altera FPGAs (that include transceivers).

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The ALSE Aurora 64B/66B is a complete and fully compliant implementation of the published protocol. It allows to interconnect Altera FPGAs to Altera and other vendors FPGAs through High-Speed Serial links, from 1Gb/s to 800 Gb/s.

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