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DesignGateway Co., Ltd.

About DesignGateway Co., Ltd.

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5

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English, Japanese

At Design Gateway, we specialize in developing application-specific FPGA IP cores that empower mission-critical systems across industries such as aerospace, automotive, finance, medical, industrial automation, and scientific research. Our solutions are built to deliver ultra-low latency, high throughput, and maximum resource efficiency, ensuring optimal performance in real-time and embedded environments.

Our engineering philosophy centers on hardware-first innovation—designing IP cores from the ground up to operate independently of CPUs and operating systems. This results in faster processing, simplified architecture, and reduced power and cost overhead—ideal for applications where reliability, determinism, and speed are non-negotiable.

Headquarters: 89/26 Amornpan 205 Tower1, 18th floor, Nathong Alley, Din Daeng, Bangkok, Krung Thep (Bangkok), 10400, Thailand

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Offering Type

offering type links Boards / SOMs / Dev Kits
offering type links Intellectual Property (IP)

Offerings

NVMe-IP core is a standalone NVMe™ Host Controller designed for seamless integration with the P-tile on Agilex™ 7 FPGA devices. It eliminates the need for a CPU or external memory, simplifying system complexity while delivering high-performance NVMe SSD interfacing—ideal for applications requiring speed, simplicity, and efficiency. Included reference designs for Altera FPGA boards help accelerate NVMe storage development, reducing both time and cost

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WireGuard10G-IP core is a high-performance hardware implementation of the WireGuard VPN protocol, delivering full 10 Gbps line-rate encryption and decryption with no CPU load or external memory required. It performs the complete WireGuard cryptographic processing entirely in programmable logic for secure and efficient FPGA-based networking applications.

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ECDSA256V-IP core is a high-performance hardware implementation of ECDSA signature verification on the NIST P-256 curve, compliant with FIPS 186-4. Designed for secure authentication in communication and IoT systems, it performs full signature verification entirely in hardware without software or external memory support.

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ChaCha20-Poly1305 IP core implements the ChaCha20 stream cipher together with the Poly1305 message authentication code (MAC), following the IETF standard for Authenticated Encryption with Associated Data (AEAD).

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Design Gateway's proprietary FPGA architecture enables stable, continuous recording at 100GbE line rate — a feat not achievable with CPU-based systems. Ideal for packet capture and analysis in high-load environments where no data loss is tolerated. The system is also scalable beyond 200GbE line rate by adding DDR memory and configuring SSDs in RAID.

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TLS1.3 IP (Transport Layer Security IP) is a CPU-less, high-performance TLS v1.3 protocol engine for FPGA acceleration, requiring no CPU or external memory. It enables maximum Gigabit Ethernet throughput for secure data transmission over 1G/10G/25G/100G networks, making it ideal for Industrial IoT, automation, aerospace, and defense applications. Our demo showcases high-throughput HTTPS upload/download with a standard web server, achieved through pure hardware logic on FPGA.

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AES256-GCM-100G IP Core (AES256GCM100GIP) implements the advanced encryption standard (AES) with 256-bit key in Galois/Counter Mode (GCM) which is widely used for Authenticated Encryption with Associated Data (AEAD) application, including IPSEC, MACSEC and TLS (Transport Layer Security) versions 1.2 and 1.3. Additionally, AES-GCM is used in fiber channel communications and storage applications.

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High-performance SHA-2 IP core supporting FIPS 180-4 compliant secure hash algorithms for authentication, secure communication, and blockchain applications.

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AES256-XTS-STG-4X IP implements the advanced encryption standard (AES) with XEX (XOR Encrypt XOR) tweakable block cipher which operates sequences of complete blocks and is suitable for protecting the confidentiality of data on NVMe™ Gen5 storage devices.

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AES256-XTS-STG-2X IP implements the advanced encryption standard (AES) with XEX (XOR Encrypt XOR) tweakable block cipher which operates sequences of complete blocks and is suitable for protecting the confidentiality of data on NVMe™ Gen4 storage devices.

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AES256-XTS-STG IP implements the advanced encryption standard (AES) with XEX (XOR Encrypt XOR) tweakable block cipher which operates sequences of complete blocks and is widely used in protecting the confidentiality of data on various storage devices with interfaces such as NVMe™ and SATA.

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AES256-GCM-10G25G IP core implements the advanced encryption standard (AES) with 256-bit key in Galois/Counter Mode (GCM) which is widely used for Authenticated Encryption with Associated Data (AEAD) application. This IP core can achieve high throughput 38.4 Gbps @300MHz, suitable to work together with our TOE10G and TOE25G IP core for high performance and secure communication applications.

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TLS1.3 IP (Transport Layer Security IP) is a CPU-less, high-performance TLS v1.3 protocol engine for FPGA acceleration, requiring no CPU or external memory. It enables maximum Gigabit Ethernet throughput for secure data transmission over 1G/10G/25G/100G networks, making it ideal for Industrial IoT, automation, aerospace, and defense applications. Our demo showcases high-throughput HTTPS upload/download with a standard web server, achieved through pure hardware logic on FPGA.

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AES256-XTS IP Core implements the advanced encryption standard (AES) with XEX Tweakable Block Cipher with Ciphertext Stealing (XTS) which is widely used in protecting the confidentiality of data on storage devices.

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AES-256SS IP specializes in ultra-high throughput and ultra-low latency. IP computes 128-bit data blocks in every 1 clock cycle. Delivering 128Mbps throughput per 1MHz such as 51.2 Gbps @ 400MHz.

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AES-256 IP supports ECB mode for both encryption and decryption, processing 128-bit data blocks in a constant 15 clock cycles. It delivers 8.53 Mbps per MHz, achieving up to 3.41 Gbps at 400 MHz. Designed to enhance the security of data storage and networking IP cores, it enables secure, efficient, and high-performance applications.

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AES-128 IP supports ECB mode for both encryption and decryption, processing 128-bit data blocks in a constant 11 clock cycles. It delivers 11.6 Mbps per MHz, achieving up to 4.65 Gbps at 400 MHz. Designed to enhance the security of data storage and networking IP cores, it enables secure, efficient, and high-performance applications.

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Design Gateway’s SHA-256 IP core provides an efficient and secure solution for implementing the SHA-256 hashing function. Optimized for hardware, this IP core offers high throughput with 7.875 Mbps per MHz, processing 512-bit data blocks in just 65 clock cycles. Its hardware-based design ensures low latency, making it suitable for applications such as secure password hashing, digital signatures, and blockchain technology. The SHA-256 IP core is easy to integrate, with a reference design and demo files available for quick evaluation on FPGA platforms.

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tCAM-IP is a high-performance, ultra-low-latency, and configurable Ternary Content-Addressable Memory IP, delivering deterministic search at 300 MSPS with a fixed latency of 7 clock cycles. It enables packet matching and filtering at up to 300 million packets per second over 40G/100G Ethernet. Ideal for applications such as packet filtering, intelligent switches/routers, deep packet inspection, and network security.

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NVMe-IP core is a standalone NVMe™ Host Controller designed for seamless integration with the integrated PCIe® Gen3 block on Altera FPGA devices. It eliminates the need for a CPU or external memory, simplifying system complexity while delivering high-performance NVMe SSD interfacing—ideal for applications requiring speed, simplicity, and efficiency. Included reference designs for Altera FPGA boards help accelerate NVMe storage development, reducing both time and cost.

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QUIC (Quick UDP Internet Connections) is a modern transport layer protocol designed to overcome the limitations of TCP while providing TLS 1.3-level security. Design Gateway's fully hardware-based QUIC-IP offloads the CPU by handling TLS 1.3 handshake, payload encryption/decryption, and managing both the QUIC and UDP/IP layers. This enables secure, high-performance communication entirely through hardware logic.

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rmNVMe-IP (Random Access & Multi-User NVMe IP) is a high-performance NVMe™ host controller optimized for high-IOPS random access applications. With pure hardware logic and no CPU involvement, it supports multiple user interfaces for simultaneous read/write access to a single NVMe SSD. Ideal for use cases like real-time sensor data fusion, OS file system offloading, and SSD testing, it offers excellent energy efficiency, performance, and low FPGA resource usage.

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raNVMe-IP (Random Access NVMe IP) is specifically optimized for random access and low latency. It can achieve over 700K IOPS for random write access on high-performance NVMe™ SSDs without CPU intervention. This makes it ideal for applications like database search, which require frequent, high-speed access to NVMe SSDs.

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NVMe-IP core is a standalone NVMe™ Host Controller designed for seamless integration with the R-tile on Agilex™ 7 FPGA devices. It eliminates the need for a CPU or external memory, simplifying system complexity while delivering high-performance NVMe SSD interfacing—ideal for applications requiring speed, simplicity, and efficiency. Included reference designs for Altera FPGA boards help accelerate NVMe storage development, reducing both time and cost.

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UDP Offloading Engine IP core is a pure hardware logic solution with no CPU involvement. The UDP25G-IP is ideal for high-performance data transmission or broadcasting over network. This IP product includes a reference design, helping reduce both development time and cost.

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exFAT IP for NVMe is designed to integrate with DG NVMe IP and the Avalon-ST Hard IP for PCIe (the PCIe Hard IP in Altera FPGA devices). This IP core provides an ideal solution for accessing NVMe devices using the exFAT file system with high-speed performance, comparable to raw data access.

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NVMeTCP25G IP is a standalone host-side NVMe over Fabric (NVMe/TCP) controller that requires no CPU or external memory. It enables high-performance remote access to NVMe-oF storage servers through simple user logic, reducing design complexity and development time. This IP allows FPGA cards or boards to connect directly to existing NVMe-oF storage infrastructure over the network with maximum performance.

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NVMeTCP10G IP is a standalone host-side NVMe over Fabric (NVMe/TCP) controller that requires no CPU or external memory. It enables high-performance remote access to NVMe-oF storage servers through simple user logic, reducing design complexity and development time. This IP allows FPGA cards or boards to connect directly to existing NVMe-oF storage infrastructure over the network with maximum performance.

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The SATA AHCI IP Core is ideal for systems with a processor running an OS that requires SATA device access for storage. By using the AHCI driver, it enables high-speed performance and full feature support. It works with embedded CPUs, such as ARM on SoC platforms, making it suitable for embedded storage systems and large-scale data acquisition systems. This IP core ensures reliable and efficient integration into diverse applications requiring high-capacity storage solutions.

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The aerospace and aviation industries demand storage solutions that are exceptionally robust, reliable, and capable of operating under extreme environmental conditions. Key requirements include high reliability in harsh conditions, resistance to shock and vibration, compliance with EMC standards, and proven, low-risk technologies. In these mission-critical applications, Design Gateway’s CPU-less SATA Host IP Core provides an ideal solution—offering a compact, efficient, and field-proven alternative to traditional storage controllers. With a strong track record in aerospace and aviation deployments, this IP core is built on a CPU-less architecture, eliminating the need for a dedicated processor. This reduces system complexity, lowers power consumption, and minimizes potential points of failure. Its compact footprint is ideal for FPGA-based designs in space- and energy-constrained environments, while still supporting scalability through multi-SATA configurations. Additionally, SATA III 6

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QUIC (Quick UDP Internet Connections) is a modern transport layer protocol designed to overcome the limitations of TCP while providing TLS 1.3-level security. Design Gateway's fully hardware-based QUIC-IP offloads the CPU by handling TLS 1.3 handshake, payload encryption/decryption, and managing both the QUIC and UDP/IP layers. This enables secure, high-performance communication entirely through hardware logic.

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AB20-U2PCI board converts 16-lane PCI Express interface to four 4-lane PCI standard U.2 interfaces, supporting PCIe Gen5 speeds. This adapter can be applied to Altera FPGA evaluation boards so that user can evaluate NVMe series IP Core operation and can use for prototype development platform.

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This adapter board converts 16-lane PCIe® interface to four 4-lane PCIe standard M.2 interfaces, supporting PCIe Gen5 speeds. This adapter can be applied to FPGA evaluation boards from Altera so that user can evaluate NVMe™ series IP Core operation and can use for prototype development platform.

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The AB18-PCIeX16 adapter board supports PCIe Gen4, making it ideal for use with high-speed NVMe Gen4 SSDs. It enables seamless evaluation of NVMe IP core series and provides a convenient interface for testing and development with Altera FPGA platforms. This adapter board simplifies the integration of NVMe SSDs, optimizing performance for high-throughput applications in real-time systems.

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This adapter board converts 8 FMC high-speed differential signals (DP0–DP7) into two 4-lane PCIe® standard M.2 interfaces. It is compatible with Altera FPGA evaluation boards featuring an HPC (High Pin Count) FMC connector, allowing users to evaluate the NVMe-IP core from Design Gateway.

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The FMC SATA RAID Board provides access for up to 10 SSD/HDDs via an FMC connector. It is also suitable for development of SATA RAID systems using FPGA development boards from Altera.

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10GbE MAC IP Core is a hardware IP core that implements the MAC layer for 10Gb Ethernet communication. It is also specifically optimized for use with Design Gateway’s TOE10G-IP and UDP10G-IP, ensuring seamless integration and maximum performance. Compared to the standard EMAC IP provided by Altera, it offers advantages in lower latency, reduced FPGA resource usage, and greater cost efficiency.

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UDP Offloading Engine IP core is a pure hardware logic solution with no CPU involvement. The UDP1G-IP is ideal for high-performance data transmission or broadcasting over network. This IP product includes a reference design, helping reduce both development time and cost.

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UDP Offloading Engine IP core is a pure hardware logic solution with no CPU involvement. The UDP10G-IP is ideal for high-performance data transmission or broadcasting over network. This IP product includes a reference design, helping reduce both development time and cost.

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TOE25G-IP Core (TCP Offloading Engine) is a pure hardware TCP/IP protocol stack engine with no CPU required. It delivers 2.5X the performance of 10GbE over a single-channel fiber optic cable. This IP core maximizes per-channel performance, increases network traffic density and scalability, and offers greater cost and power efficiency per bit compared to traditional 10GbE/40GbE network technologies.

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UDP Offloading Engine IP core is a pure hardware logic solution with no CPU involvement. The UDP40G-IP is ideal for high-performance data transmission or broadcasting over network. This IP product includes a reference design, helping reduce both development time and cost.

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UDP Offloading Engine IP core is a pure hardware logic solution with no CPU involvement. The UDP100G-IP is ideal for high-performance data transmission or broadcasting over network. This IP product includes a reference design, helping reduce both development time and cost.

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TOE200G Advanced IP core (TOE200GADV-IP) is a groundbreaking hardware-based TCP/IP engine that achieves record-breaking data transfer speeds exceeding 24 GB/s. Unlike traditional CPU- or memory-dependent solutions, it uses pure hardwired logic and 200G Ethernet Hard IP on an FPGA board to eliminate bottlenecks. This architecture enables unmatched TCP processing performance for high-speed data applications.

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100GbE TCP Offloading Engine (TOE100G-IP) IP core is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU is required. TOE100G-IP built by pure hardwired logic can take place of such extra CPU for TCP protocol management.

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40GbE TCP Offloading Engine (TOE40G-IP) IPcore is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU is required. TOE40G-IP built by pure hardwired logic can take place of such extra CPU for TCP protocol management.

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muNVMe-IP (Multi-user NVMe IP) is designed and optimized for simultaneous access to a single NVMe™ SSD by multiple data streams. It delivers near-maximum SSD throughput for both mixed and same-direction read/write operations. Ideal for applications requiring high performance and multiple data streams or sequential access via pure hardware logic without CPU or OS.

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10GbE TCP Offloading Engine (TOE10G) IP core is the epochal solution implemented without CPU. Typically, TCP/IP stack consumes high valuable resource of CPU workloads. With its pure hardware logic, TOE10G IP can entirely take over the TCP/IP stack operation with high proven throughput for 10GbE communication.

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The TCP Offloading Engine (TOE1G) IP core is an innovative, CPU-free solution for TCP/IP processing. Traditionally, TCP handling is complex and requires expensive high-end CPUs. TOE1G-IP offloads all TCP/IP functions to pure hardware logic, enabling high-speed performance without software overhead.

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