Computer Aided Software Technologies, Inc (dba CAST)

The CSENT-RX core implements a receiver for the Single Edge Nibble Transmission (SENT) protocol. It complies with the SAE J2716 standard and supports both synchronous and asynchronous sensors. It can be used for receiving data from one or multiple sensors. The CSENT-RX provides access to its data registers via a 32-bit APB, or AXI4-Lite bus interface. The core provides a glitch filter on the serial data input and has data mapping functionality on received data to offload the connected host from data formatting. The received data are accessible via the register interface. The core is also capable of generating trigger pulses requesting synchronous sensors to send data. A set of handshaking signals facilitates the integration with an external DMA controller. The CSENT-RX core is available in two versions: Standard and Safety-Enhanced: ISO-26262 ASIL B Ready.

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The CSENT-TX core implements a transmitter for the Single Edge Nibble Transmission (SENT) protocol. It complies with the SAE J2716 standard and supports both synchronous and asynchronous transmissions. In asynchronous mode, the core autonomously initiates transmission, as data become available in its input-data register. Under synchronous mode, transmission is triggered by either the host system via the core’s control registers, or when the core receives a valid master trigger pulse via the SENT interface. The core reports its status using two signals, one indicating that a transmission is in progress, and a second one reporting the completion of a frame's transmission. The CSENT-TX also provides access to its registers via a 32-bit APB, or an AXI4-Lite or a generic interface. The core contains no latches or tri-states, is fully synchronous with a single clock domain, and includes no multicycle or false paths. The CSENT-TX core has been rigorously verified and is production proven.

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The PSI5-HOST IP core is a configurable automotive Peripheral Sensor Interface (PSI5) host controller implementing the ECU side of PSI5 communication systems, supporting PSI5 Specification v2.3 with backward compatibility to PSI5 v1.3. It enables robust communication between ECUs and automotive sensors using a low-cost two-wire interface over sensor power lines. The core supports synchronous and asynchronous modes, ECU-to-sensor downstream communication via tooth-gap or pulse-width encoding, and sensor-to-ECU Manchester-coded upstream messaging. Safety-oriented features include programmable watchdog timing slot monitoring, receive frame timestamps, and CRC or parity-based data protection per the PSI5 specification, enabling integration into ISO 26262-oriented systems. Register access is performed via an AMBA APB interface. The silicon-proven core is rigorously verified, with optional functional safety documents and diagnostic features aiding ISO 26262 integration.

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The MSC-CTRL IP core implements a high-speed serial interface controller designed to connect an SoC to external power devices or sensors. It implements the Microsecond Channel (MSC) protocol and acts as a bus master for downstream and as a bus slave for upstream transfers. The MSC-CTRL is integrated to peripherals via high-speed synchronous downstream and low-speed asynchronous upstream channels. It supports up to four slave devices in the MSC mode, advanced features, fragmented command frames, and higher upstream baud rates, provide robust communication in a network of dedicated sensors or devices. The IP includes a 32-bit AMBA® APB4 subordinate interface and includes trigger signals to facilitate easy integration with an external DMA controller. The silicon-proven MSC-CTRL core is designed to industry best practices and has been rigorously verified. Optional functional safety documents facilitate ISO 26262 ASIL B standard.

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LZ4SNP-D is a custom hardware implementation of a lossless data decompression engine for the LZ4 and Snappy compression algorithms. The core receives compressed files, automatically detects the LZ4 or Snappy format, and outputs the decompressed data.

The core features fast processing with low latency and high throughput. In its default configuration, LZ4SNP-D outputs up to 7.8 bytes of decompressed data per clock cycle and can be clocked at frequencies exceeding 1 GHz in modern ASIC technologies. Designers can scale the throughput by instantiating the core multiple times to achieve throughput rates exceeding 100Gbps. The processing latency is approximately 30 clock cycles.

The decompression core operates on a standalone basis—offloading the host CPU from the demanding task of data decompression—and has been designed for easy integration and use. No preprocessing of the incoming compressed files is required, as the core parses the file headers, and checks the input files for errors.

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ZipAccel-D is a custom hardware implementation of a lossless data decompression engine that complies with the Inflate/Deflate, GZIP/GUNZIP, and ZLIB compression standards.

The core features fast processing, with low latency and high throughput. On average the core outputs three bytes of decompressed data per clock cycle. Designers can scale the throughput further by instantiating the core multiple times to achieve throughput rates exceeding 100Gbps. The latency is in the order of a few tens of clock cycles for blocks coded with static Huffman tables, and typically less than 2,000 cycles for blocks encoded with dynamic Huffman tables.

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LZ4SNP-C is a custom hardware implementation of a lossless data compression engine that complies with the LZ4 and Snappy compression standards. The core receives uncompressed input files and produces compressed files. No post-processing of the compressed files is required, as the core encapsulates the compressed data payload with the proper headers and footers.

The core’s flexible architecture enables fine-tuning of its compression efficiency and throughput to match the requirements of the end application. More than one block compression engine can be internally instantiated to scale throughput, while block and history window sizes can be adjusted to optimize either hardware resources utilization or compression efficiency.

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ZipAccel-C is a custom hardware implementation of a lossless data compression engine that complies with the Deflate, GZIP, and ZLIB compression standards.

The core receives uncompressed input files and produces compressed files. No post-processing of the compressed files is required, as the core encapsulates the compressed data payload with the proper headers and footers. Input files can be segmented, and segments from different files can be interleaved at the core’s input.

The core’s flexible architecture enables fine-tuning of its compression efficiency, throughput, and latency to match the requirements of the end application.

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The JPEG-LS-E core is a low-power, high-efficient image compression engine compliant with JPEG-LS (ISO/IEC 14495-1). Based on the LOCO-I algorithm, it achieves compression ratios comparable or superior to JPEG2000 in lossless mode, while requiring far less area & memory thanks to its low complexity & line-based processing. Its Near-Lossless mode enables higher compression ratios with visually lossless quality, letting users define the max pixel error. It delivers full JPEG-LS compression efficiency in a compact, easy-to-integrate hardware block. It connects through AMBA® interfaces: AXI4-Stream for image input & compressed output, & a 32-bit APB for control & status. Once configured, it can process unlimited images without host intervention, with optional metadata or timestamps inserted via a dedicated streaming port. The core’s robustness has been proven through extensive verification & silicon validation & is delivered with a full verification environment & bit-accurate SW model.

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The PCI-T32MF is a target-only PCI interface core compliant with the PCI 2.3 specification, supporting a 32-bit address/data bus and operating at up to 33 MHz. It allows one to eight independent PCI functions per chip, each with 64 to 256 bytes of PCI Configuration Space and up to six Base Address Registers, decoding I/O and Memory space from 16 bytes to 4GB. Developed with over 20 years of CAST PCI IP expertise, the core is optimized for easy reuse, integration, and technology mapping. It is available as synthesizable RTL or a targeted FPGA netlist, with full support for rapid implementation.

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Implements an interface and controller for communicating between smart cards and host systems using a variety of standard system interfaces. The SCR supports the ISO/IEC 7816-3:2006 and EMV 4.3 specifications, which define the electrical signals and transmission protocols for smart cards (also known as integrated circuit cards). It acts as a communication controller, passing data to and from the host system and the smart card. It is fully-featured, and can activate and deactivate cards, perform cold/warm resets, handle ATR response reception, and execute other essential functions.

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The JPEG-D-S IP core is a compact, high-performance hardware JPEG decoder supporting the Baseline Sequential DCT mode of ISO/IEC 10918-1. It decompresses JPEG images and Motion-JPEG payloads, handling 8-bit samples and up to 4 components in all common subsampling formats. Processing 1 sample/cycle, it can decode multiple Full-HD channels even in cost-sensitive FPGAs. One of the smallest decoders, it uses about 4,000 ALMs in Altera FPGAs. Once programmed, it operates standalone, parsing markers and decompressing without host intervention. It reports resolution, subsampling, and depth for proper post-processing or display. Integration is simple via AMBA®: AXI Streaming for pixels/data and a 32-bit APB slave for registers. CAST offers integration services delivering complete JPEG subsystems with decoders, video interfaces, networking stacks, or other IP. Designed with best practices, its proven reliability is backed by verification, production use, and a bit-accurate software model.

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Implements a UDP/IP hardware protocol stack enabling high-speed LAN or point-to-point communication and media streaming up to 10 Gbps, even in processor-less SoC designs. Offloads the host CPU from UDP/IP encapsulation. All network parameters (IP addresses, UDP ports, MAC) are runtime programmable, supporting static or DHCP-assigned IP. Includes ARP for multi-access networks, ICMP ping for connectivity tests, and IEEE 802.1Q VLAN tagging. Supports up to 32 transmit and 32 receive streaming interfaces (channels), each independently configurable for IP, port, multicast address, and unicast/multicast mode. Integrates easily in SoC designs via AXI4-Stream, Avalon-ST, AHB, AXI, Avalon-MM, or Wishbone interfaces, with data exchange via streaming ports or memory-mapped registers. Ideal for real-time networking, video streaming, and industrial applications requiring low-latency, deterministic UDP/IP communication in FPGA or ASIC designs.

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The JPEG-E-S IP core supports the Baseline Sequential DCT modes of ISO/IEC 10918-1, implementing a high-performance, area-efficient hardware JPEG encoder with low latency. It produces compressed JPEG images and Motion-JPEG payloads, handling 8-bit color samples and up to four components in all common subsampling formats. Processing one sample per cycle, it can compress multiple Full-HD channels even in low-cost FPGAs. Once configured, it operates standalone without host intervention. Integration is simple via AMBA®: AXI Streaming for pixels/compressed data and a 32-bit APB slave for registers. Optional AXI Streaming allows timestamps or metadata insertion. CAST offers IP Integration Services delivering complete JPEG subsystems with video interfaces, UDP/IP or Transport Stream stacks, and other IP. Designed with industry best practices, its reliability is proven through verification, production use, and a bit-accurate software model.

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The JPEG-EX-S IP core supports Baseline and Extended Sequential DCT modes of ISO/IEC 10918-1, implementing a high-performance, area-efficient HW JPEG encoder for ASIC or FPGA with low latency. It produces compressed JPEG images and Motion-JPEG payloads, handling 8- or 12-bit samples and up to four components in all common subsampling formats. Processing one sample per cycle, it can compress multiple Full-HD channels even in low-cost FPGAs. One of the smallest encoders, it uses ~80k gates in ASICs. Once programmed, it operates standalone without host assistance. Integration is simple via AMBA®: AXI Streaming for pixels/data and 32-bit APB for registers, with optional AXI Streaming for timestamps or metadata. CAST offers IP Integration Services delivering complete JPEG subsystems with decoders, video interfaces, UDP/IP or Transport Stream stacks, or other IP. Designed to industry best practices, reliability is proven by verification, production use, and a bit-accurate software model.

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The PCI-M32 implements a master/target PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up to 33 MHz PCI clock.

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The PCI-M32MF is a PCI 2.3-compliant master/target core supporting a 32-bit address/data bus at up to 33 MHz. It enables 1 to 8 independent PCI functions per chip, each with 64–256 bytes of Configuration Space and up to six Base Address Registers, supporting I/O and Memory decoding from 16 bytes to 4 GB. Backed by over 20 years of CAST PCI IP expertise, the core is designed for easy reuse and integration, and is available as synthesizable RTL or FPGA netlist with comprehensive deliverables.

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The AES-P encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. Two architectural versions are available to suit system requirements. The Standard version (AES-P-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-P-F) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. It can be programmed to use any of the following cipher modes: CBC, CTR, ECB, and OFB. The core works with a pre-expanded key, or with optional key expansion logic. The AES-P core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.

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The AES encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. Two architectural versions are available to suit system requirements. The Standard version (AES-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-F) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. Various cipher modes can be supported (CBC, CFB, CTR, ECB, LRW, and OFB). The core works with a pre-expanded key, or with optional key expansion logic. The AES core is a fully synchronous design and has been evaluated in a variety of technologies. It is available optimized for ASICs or FPGAs, with complete deliverables.

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The CAST ASRC (Audio Sample Rate Converter) is a compact, high-performance IP core that delivers precise digital audio conversion across a wide range of sample rates (8 kHz to 192kHz) while preserving signal integrity and minimizing distortion. Supporting both asynchronous and synchronous modes, it ensures seamless real-time streaming or high-speed batch processing for applications in professional audio, broadcast, telecommunications, automotive infotainment, gaming, and VR. The ASRC handles tens to hundreds of TDM channels, achieving ultra-low distortion with THD+N averaging -130 dB. With sub-100ms sync time and minimal latency, it provides transparent, studio-grade 24-bit audio conversion. Designed for easy integration into ASICs or FPGAs, it features AXI4-Stream for audio data, AXI-Lite/APB control interfaces, and optimized resource usage for cost-sensitive environments. Deliverables include Verilog RTL/netlist, testbenches, drivers, and documentation for rapid deployment

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The PCI-T32 is a 32-bit target PCI interface core compliant with PCI 2.3, operating at up to 33 MHz. It includes 64 bytes of PCI Configuration Space, expandable to 256 bytes, and supports six Base Address Registers for I/O or Memory decoding from 16 bytes to 4 GB. Supported commands include Configuration, Memory, and I/O Reads/Writes, as well as MRM, MRL, and MWI. Built on over 15 years of CAST PCI IP experience, the core is designed for easy reuse and integration. It is available in synthesizable RTL or as an FPGA netlist, with full integration support.

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The ASCON-F IP is a compact, high-throughput HW core implementing the lightweight authenticated encryption with associated data (AEAD) & hashing algorithms of the Ascon v1.2 spec. A single instance supports encryption & decryption with Ascon-128 & Ascon-128a, as well as cryptographic hashing with Ascon-Hash & Ascon-Hasha. Operation mode, key, and nonce values are run-time programmable & can change per input block. The core provides simple I/O I/F, optionally bridged to AXI4-Stream or AXI4 Memory Mapped ports through CAST bridges. It synthesizes to ~11k gates & runs at over 2GHz in modern ASIC technologies. Excluding padding & initialization, throughput ranges from 5.3 to 16 bits/cycle, or 10.6 to 32Gbps at 2GHz, with higher throughput possible by instantiating multiple cores. Easy to use & integrate, following best coding & verification practices, has no multi-cycle or false paths, uses only rising-edge D flip-flops, no tri-states or SRAMs, and operates in a single clock/reset domain.

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The H16450S is a standard UART providing 100% software compatibility with the popular Texas Instruments 16450 device. It performs serial-to-parallel conversion on data originating from modems or other serial devices, and performs parallel-to-serial conversion on data from a CPU to these devices. Developed for easy reuse in ASIC and FPGA applications, the H16450S is available optimized for several technologies with competitive utilization and performance characteristics.

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The H16750S is a standard UART providing 100% software compatibility with the popular Texas Instruments 16750 device. It performs serial-to-parallel conversion on data originating from modems or other serial devices, and performs parallel-to-serial conversion on data from a CPU to these devices. The H16750S can be run in either 16450-compatible character mode or FIFO mode, where an internal FIFO relieves the CPU of excessive software overhead. An IrDA-compliant serial data port may be used for infrared communication. Developed for easy reuse in FPGA or ASIC applications, the H16750S is available optimized for several technologies with competitive utilization and performance characteristics

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The JPEG-DX-S IP core is an area-efficient high-performance JPEG decoder supporting Baseline and Extended Sequential DCT modes of ISO/IEC 10918-1. It decodes JPEG and Motion-JPEG payloads, supporting 8- or 12-bit samples and up to four components in standard subsampling formats. Processing one sample per cycle, it can handle multiple Full-HD channels in cost-sensitive FPGAs. One of the smallest available, it requires ~76k gates in ASICs. Once configured, the core runs standalone, parsing markers and decompressing without host intervention. It reports resolution, subsampling, and depth for correct post-processing. Integration is simple via AMBA®: AXI-Stream for pixels/data and a 32-bit APB for registers. CAST offers integration services delivering complete JPEG subsystems (decoders, video interfaces, networking stacks, etc.). Designed to industry best practices, quality is proven by verification, silicon validation, and a bit-accurate software model. Scan-ready, LINT-clean, production.

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The I2C-SMBUS core is a serial interface controller for the Inter-Integrated Circuit (I2C) and System Management Bus (SMBus), and is also suitable for the Power Management Bus (PMBus). It can operate as a bus master or slave, with simple programming and easy integration. An arbitration mechanism enables use in multi-master systems, while SMBus clock synchronization supports fast-master/slow-slave communication. The core prevents deadlocks by detecting timeouts and errors and includes glitch filtering on the serial line. Control, status, and data registers are accessible via AMBA APB or a generic memory-mapped interface. Designed for reuse in ASIC and FPGA implementations, it is microcode-free and uses only rising-edge-triggered flip-flops with configurable reset types. The design avoids tri-states, ensuring straightforward scan insertion and efficient implementation in embedded systems.

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The JPEG-XL-E implements an image compression engine compliant to the JPEG XL, ISO/IEC 18181 standard. Leveraging the advanced coding tools of the JPEG XL standard, the core achieves substantially higher compression efficiency than legacy JPEG while requiring fewer hardware resources than JPEG 2000 and comparable codecs. By incorporating algorithms optimized for human visual perception, it delivers exceptional performance for high dynamic range (HDR) and wide color gamut (WCG) imagery. Thanks to its efficient architecture, the compact encoder core achieves a latency of just one frame and a processing throughput of one sample per clock cycle. A single instance can encode 4K-resolution images in real time, while multiple cores can be instantiated in parallel to support higher resolutions.

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The MAC-SEC-MG from CAST is a high-performance hardware MACsec IP core designed to provide robust security for 2-16.75 Gbps Ethernet networks. It fully implements the IEEE 802.1AE-2018 and IEEE 802.1AEbw standards, supporting GCM-AES and GCM-AES-XPN encryption modes with 128- and 256-bit keys. The core features a 128-bit wide data path and operates at line speed in full-duplex mode, ensuring low-latency and secure communication. It supports up to 64k security associations and multiple security channels and entities, making it suitable for both simple LAN deployments and complex WAN architectures. MAC-SEC-MG integrates easily with Ethernet MACs, including CAST’s Low-Latency eMAC, and can work alongside networking protocol stacks such as UDP/IP and TCP/IP. Its standardized interfaces and high configurability make it ideal for automotive, industrial, and IoT edge applications, providing reliable encryption, authentication, and integrity protection for sensitive Ethernet traffic.

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The I3C-T core is a flexible, target-only MIPI® I3C controller compliant with the latest I3C-BasicSM specification. Supporting SDR communication while tolerating HDR traffic, it interoperates with legacy I2C devices and can optionally function as an I2C target. The core autonomously handles relevant Common Command Codes (CCCs), supports dynamic or static addressing, Hot-Join, and In-Band Interrupts. It offers two operating modes: normal mode, where data transfers use an APB subordinate interface, and I3C-to-AHB bridging mode, where private I3C/I2C transactions are automatically converted into AHB accesses for remote monitoring, configuration, debug, or data exchange without software intervention. With both synthesis-time and run-time configurability, the I3C-T adapts to application needs while minimizing footprint. Designed with best coding practices, clean clock domain crossings, and FPGA validation, it ensures reliable, low-risk integration.

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The TSN-SW implements a highly flexible, low-latency, multiport TSN Ethernet switch. It supports the hardware functionality for Ethernet bridging according to the IEEE 802.1Q standard and implements the essential TSN timing synchronization and traffic-shaping protocols (i.e. IEEE 802.1AS-2020, 802.1Qav, 802.1Qbv, and 802.1Qbu, 802.1br). Enhanced reliability features can also be supported, using the optional hardware modules for Frame Replication and Elimination for Reliability (IEEE 802.1CB) and Per-Stream Filtering and Policing (IEEE 802.1Qci). Featuring a configurable number of ports, the Layer-2 switch operates in cut-through mode at wire speed and can provide sub-microsecond port-to-port latency. The core is hence suitable for applications with demanding real-time requirements.

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"The TSN-SE is a highly configurable two-port Switched Endpoint Controller IP core tailored for Time-Sensitive Networking (TSN) Ethernet systems. It embeds hardware support for 802.1AS-2020 timing synchronization, 802.1Qav/Qbv traffic shaping, 802.1Qbu/802.3br frame preemption, plus two low-latency Ethernet MACs. Optional modules enable enhanced reliability with 802.1CB frame replication and elimination, and 802.1Qci per-stream filtering and policing. Designed for daisy-chained or ring topologies and bridged endpoints, TSN-SE delivers precise, deterministic ingress/egress latency via cut-through switching and minimal buffering, simplifying time-aware application development. It provides real-time timing data timestamps, alarms, and allows dynamic traffic-shaping configuration. Integration is seamless via standard AMBA® interfaces: a 32-bit APB bus for control/status, and 32-bit AXI-Streaming for packet I/O. Optional DMA engine and software stacks are also available.

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The TSN-EP implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking (TSN) standards. It integrates hardware stacks for timing synchronization (IEEE 802.1AS-2020) and traffic shaping (IEEE 802.1Qav and 802.1Qbv), frame-preemption (IEEE 802.1Qbu and IEEE 802.3br) and a low-latency Ethernet MAC. Enhanced reliability features can also be sup ported, using the optional hardware modules for Frame Replication and Elimination for Reliability (IEEE 802.1CB) and Per-Stream Filtering and Policing (IEEE 802.1Qci).

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The I2S-TDM IP core is a configurable, full-duplex, multi-channel serial audio transceiver supporting both Inter-IC Sound (I2S) and Time-Division Multiplexed (TDM) interfaces. It can operate as either controller (master) or target (slave), exchanging audio samples over programmable serial lines. Designers can configure parameters such as sample width (2–32 bits), sample rate, frame format, number of channels, and allocation per line at run time, while synthesis-time options define maximum supported channels and lines. Integration is simplified with APB or AXI4-Lite control interfaces and AXI4-Stream for audio data, with clean clock domain crossings. The core is delivered as Verilog RTL or FPGA netlist, with testbench, scripts, drivers, and documentation, and typically uses about 10K gates for an 8-channel configuration.

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The I3C-SC core is a versatile MIPI® I3C Secondary Controller compliant with the latest I3C BasicSM specification. It can operate as a bus controller or target, supporting SDR communication while tolerating HDR traffic, and coexisting with legacy I2C devices. As a target, it autonomously handles Common Command Codes (CCCs), supports dynamic or static addressing, Hot-Join, and In-Band Interrupts. The core offers two operating modes: normal mode, where data is exchanged via an APB subordinate interface, and I3C-to-AHB bridging mode, where private I3C/I2C transfers are converted into AHB transactions for remote monitoring, configuration, or data exchange without software intervention. Flexible synthesis-time and run-time options allow customization of features, size, and behavior. With industry-best design practices, clean clock domain crossings, and FPGA validation, the I3C-SC ensures reliable, low-risk integration into ASIC or FPGA designs.

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The TCPIP-1G/10G core is a complete TCP/IP hardware protocol stack, enabling systems to connect to IP networks and exchange TCP data without a host processor. Acting as server or client, it autonomously opens, maintains, and closes TCP connections. Network parameters are configured via control registers, while data is exchanged over streaming interfaces. The core is highly configurable: up to 32,768 simultaneous TCP sessions can be supported, or just one for minimal area designs. Options include a DHCP client, reassembly of out-of-order packets, and integration of a UDP hardware stack with IGMPv3 multicast. Users may select cut-through mode for ultra-low latency and minimal buffering, or store-and-forward mode for verified, in-order delivery. Available in RTL or FPGA netlist form, the core is rigorously verified and provided with testbench, synthesis/simulation scripts, and full documentation, making it ideal for applications ranging from servers to edge devices.

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The H264-E-BPF IP core is a video encoder supporting the Constrained Baseline Profile of the ISO/IEC 14496-10/ITU-T H.264 standard. The H264-E-BPF encoder requires less silicon area than most equally capable hardware H.264 encoders—approximately 250K gates—allowing for very cost-effective implementations. Its small silicon footprint, low external memory bandwidth requirements, and zero software overhead enable high-throughput H.264 coding at an extremely low energy cost.

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The xSPI-MC is a versatile memory controller supporting JEDEC xSPI, HyperBus™, and Xccela™ standards, as well as proprietary SPI protocols for Flash and PSRAM. It enables easy device detection, direct boot, and operation in multiple modes: Slave (AHB slave access), DMA (with internal DMA engine), Access In-Place (AIP) via AHB/AXI, and Boot-Image copy after reset. Compatible with single to 16x SPI devices, it offers flexible configuration through registers or an auto-configuration feature using a device list. Highly customizable via Verilog defines, it allows selection of DMA, auto-configuration, and device count. Delivered with a synthesizable soft-PHY, it is FPGA/ASIC ready and requires no process-specific dependencies.

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"The CAN-CTRL is a CAN bus controller compliant to Classical CAN, CAN FD, and CAN XL. The core is easy to use and integrate, featuring programmable interrupts, data and baud rates; and a configurable number of independently programmable acceptance filters. It implements a flexible buffering scheme, allowing fine-tuning of the core size to satisfy the requirements of each specific application.The number of receive buffers is synthesis-time configurable. Two types of transmit buffers are implemented: a high-priority primary transmit buffer (PTB) and a lower-priority secondary transmit buffer (STB). Finally, the CAN-CTRL provides error analysis, diagnosis, maintenance, and optimization features. The CAN-CTRL is available in two versions: Standard and Safety-Enhanced. The Safety-Enhanced version implements ECC for SRAMs protection and uses spatial redundancy for protecting the inner logic of the core. The Safety-Enhanced versions are certified as ISO-26262 ASIL-D Ready. "

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The H16550S is a standard UART providing 100% software compatibility with the popular Texas Instruments 16550 device. It performs serial-to-parallel conversion on data originating from modems or other serial devices, and performs parallel-to-serial conversion on data from a CPU to these devices. The H16550S can be run in either 16450-compatible character mode or in 16550-compatible FIFO mode, where an internal FIFO relieves the CPU of excessive software overhead. Developed for easy reuse in FPGA or ASIC applications, the H16550S is available optimized for several technologies with competitive utilization and performance characteristics.

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The JPEG-LS-D core, a highly efficient & low-power, lossless & near-lossless image decompression engine & compliant to the JPEG-LS, ISO/IEC 14495-1 standard, can decompress any JPEG-LS stream or JPEG-LS payload of image container formats. It accepts compressed streams of images with up to 16-bit per color samples & up to 4 color components, in all widely used color subsampling formats, supporting oversize image dimension parameters & resolutions higher than 64k x 64k. With standalone operation, parsing marker segments & decompressing coded data, the core reports back the image format. APP or COM marker segments are also passed to the system via a dedicated interface. Straightforard integration, standardized AMBA® I/F (compressed data & outputs pixel data, frame format information, APP or COM marker via AXI4-Stream - access to control & status registers via 32-bit APB). A wrapper that bridges the AXI-Stream interfaces to AXI4 can optionally be delivered with the core.

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The SHA-3 IP core is a high-throughput, area-efficient hardware accelerator for SHA-3 cryptographic hashing, compliant with NIST FIPS 180-4 and FIPS 202. It operates independently of a host processor, using AMBA® AXI4-Stream interfaces for input and output. An optional AXI4-Stream to AXI4 Memory Mapped bridge, with or without DMA, can be used. A single core instance implements all fixed-length and extendable-output hash functions, with function and output length (up to 2 GB) selectable at runtime per input message. The core is highly configurable at synthesis, including bus width and SHA-3 permutation rounds per cycle, enabling throughput–area trade-offs. One permutation per cycle processes 50 bits per cycle, scaling to over 100 Gbps with multiple permutations in modern ASICs. Fully synchronous, single-clock, scan-ready, LINT-clean, it uses only rising-edge flip-flops, with no false or multi-cycle paths, simplifying integration and verification.

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The TSN-EP-10G is a highly configurable TSN Ethernet Endpoint Controller IP core designed to streamline the implementation of Time-Sensitive Networking endpoints. It provides hardware support for 802.1AS-2020, 802.1Qav, 802.1Qbv, optional 802.1Qci and 802.1Qcc. It includes a low-latency Ethernet MAC with XGMII PHY interface and AXI-Stream Host interface. The core delivers precise, deterministic latencies with minimal host software required and provides real-time timing information along with dynamic traffic-shaping adjustments. Designed for simple integration, TSN-EP-10G uses standard AMBA® interfaces: a 32-bit APB for CSR and a 128-bit AXI-Streaming interface for data packets. Optional DMA is also available. Delivered as synthesizable RTL or FPGA netlist, it includes testbenches, sample scripts, documentation and a lightweight gPTP for FreeRTOS and Linux. Suitable for automotive, industrial, aerospace, and other applications requiring low-latency, deterministic TSN communication.

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The L8051XC1 is an MCS®51-compatible microcontroller core designed to match the timing and peripherals of legacy 8051-based systems. It supports instruction execution every 12, 6, or 4 clock cycles and includes user-selectable architectural extensions such as multiple data pointers, a multiply/divide unit, and a power management unit. The core can be coupled with peripherals that match the behavior of those from legacy vendors like Intel, NXP, Infineon, Maxim, and TI. Several pre-configured versions are available, along with options for customization. It supports legacy code and modern development through CAST’s on-chip debugging features and compatibility with IAR Embedded Workbench and Keil uVision™ IDEs. With design experience dating back to 1997 and hundreds of 8051 IP customers, CAST ensures that the core is optimized for easy ASIC/FPGA reuse. It is strictly synchronous, with positive-edge clocking and no internal tri-states. At 65nm, the core uses just 7.9K–20K gates.

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The AES-GCM IP core implements NIST Advanced Encryption Standard (AES) in Galois Counter Mode (GCM). GCM is an authenticate-and-encrypt block cipher mode where a Galois Field (GF) multiplier/accumulator is utilized to generate an authentication tag while CTR (Counter) mode is used to encrypt. The core processes 128-bit blocks and is programmable for 128-, 192-, and 256-bit keys. Four architectural versions are available to suit system requirements. The Standard version (AES-GCM-S), more compact using a 32-bit datapath, requires 44/52/60 clocks for each data block (128/192/256-bit key, respectively). The Fast version (AES-GCM-F) achieves higher throughput using a 128-bit datapath and requires 11/13/15 clocks for each data block depending on key size. For high-throughput applications there are two additional versions. The High Throughput AES-GCM-X can process 128 bits/cycle and the Higher Throughput AES-GCM-X2 can process 256 bits/cycle respectively independent of the key size.

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The AES-CCM IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. Two architectural versions are available to suit system requirements. The Standard version (AES-CCM-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-CCM-F) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. CCM stands for Counter with CBC-MAC mode. CCM is a generic authenticate-and-encrypt block cipher mode. CBC-MAC is utilized to generate an authentication string while CTR mode is used to encrypt. The AES-CCM core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.

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Implements a UDP/IP hardware protocol stack enabling high-speed LAN or point-to-point communication and media streaming up to 25 Gbps, even in processor-less SoC designs. Offloads the host CPU from UDP/IP encapsulation. All network parameters (IP addresses, UDP ports, MAC) are runtime programmable, supporting static or DHCP-assigned IP. Includes ARP for multi-access networks, ICMP ping for connectivity tests, and IEEE 802.1Q VLAN tagging. Supports up to 32 transmit and 32 receive streaming interfaces (channels), each independently configurable for IP, port, multicast address, and unicast/multicast mode. Integrates easily in SoC designs via AXI4-Stream, Avalon-ST, AHB, AXI, Avalon-MM, or Wishbone interfaces, with data exchange via streaming ports or memory-mapped registers. Ideal for real-time networking, video streaming, and industrial applications requiring low-latency, deterministic UDP/IP communication in FPGA or ASIC designs.

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The HSDLC IP core implements HDLC and SDLC protocols, based on the Intel® 8XC152 GSC in SDLC mode with added HDLC and proprietary frame support. It connects as a peripheral to a host processor via APB or 80C51-like interfaces, with full interrupt support for efficient operation. Flexible design allows two independent TX/RX interfaces with support for full- or half-duplex, hardware flow control (RTS/CTS), collision detection, and programmable baud rates. Receive clock is derived from incoming data or supplied externally. Available in Normal and Safety-Enhanced (TMR, DO-254 DAL-A) versions, the HSDLC core is fully synchronous, scan-ready, verified, and delivered in Verilog RTL or FPGA netlist. Deliverables include scripts, testbench, and complete documentation.

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This JPEG compression IP core supports the Baseline and Extended Sequential DCT of ISO/IEC 10918-1 standard. It is scalable and ultra-high-performance, while handles extremely high pixel rates using significantly fewer silicon resources and less power than encoders for video compression standards such as HEVC/H,265, DSC, AVC/H.264, or JPEG200. The JPEG-EX-F encoder accepts images with up to 12-bit color samples and up to four color components, in all widely-used color subsampling formats. It can process from 2 to 32 color samples per clock cycle enabling it to compress UHD (4K/8K) video and/or very high frame video. Standalone operation, once programmed, with straightforward SoC integration (standard AMBA I/F - AXI Streaming & APB Slave). CAST’s IP Integration Services are also available for JPEG subsystems (the JPEG decoder with video interface controllers, Hardware UDPIP or Transport Stream networking stacks, or other IP cores available from CAST).

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The LIN-CTRL core is a controller that transmits and receives complete LIN frames to perform serial communication according to the LIN Protocol Specification. It can be configured before the synthesis to operate as a master, slave or include both profiles. When configured with both – master and slave, then at run-time, the LIN-CTRL can operate either as a master or as a slave and supports versions 1.3, 2.0, 2.1, and 2.2 of the LIN protocol. The message transfers can be controlled via a microcontroller interface and a LIN transceiver is needed for the connection to the LIN bus. The LIN-CTRL core is a microcode-free design developed for reuse in ASIC and FPGA implementations. The robustly verified core has been production-proven multiple times. The LIN controller core is available in two versions: Standard, and Safety-Enhanced. The Safety-Enhanced versions are certified as ISO-26262 ASIL-D Ready.

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The SPMI-CTRL IP core implements the MIPI System Power Management Interface (SPMI) v2.0 protocol, enabling efficient and standardized communication between power management ICs (PMICs) and other components in complex SoCs. It can operate as either a controller or a target, making it flexible for a wide range of designs. The core autonomously manages critical protocol tasks such as command execution, ACK/NACK responses, arbitration, and address/data parity, minimizing host processor involvement and reducing system overhead. Its architecture is optimized for reliability and interoperability, ensuring robust power control and communication in mobile, automotive, and IoT devices. Supporting both single-master and multi-master configurations, the SPMI-CTRL offers scalability to meet diverse system requirements. Easy integration with standard system buses and configurability make it a practical, high-performance solution for developers implementing advanced power management networks.

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This JPEG decompression IP core supports the Baseline & Extended Sequential DCT modes of the ISO/IEC 10918-1. It is scalable and ultra-high-performance, while handles extremely high pixel rates of JPEG images and video payload for Motion-JPEG container formats. It accepts compressed streams of images with 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats. It can process from 2 to 32 color samples per clock cycle. Paired with the JPEG-EX-F Encoder Core provide an extremely cost-effective solution. Standalone operation, once programmed, parsing marker segments, decompressing coded data and reporting back the image format. SoC integration is straightforward (standard AMBA I/F - AXI Streaming & APB Slave). CAST’s IP Integration Services are also available for JPEG subsystems (the JPEG decoder with video interface controllers, Hardware UDPIP or Transport Stream networking stacks, or other IP cores available from CAST).

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The TCPIP-1G/10G core is a complete hardware TCP/IP stack that supports up to 32k sessions, DHCP, UDP with multicast, and offers configurable low-latency cut-through or reliable store-and-forward modes.

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Implements a UDP/IP hardware protocol stack enabling high-speed LAN or point-to-point communication and media streaming up to 100 Gbps, even in processor-less SoC designs. Offloads the host CPU from UDP/IP encapsulation. All network parameters (IP addresses, UDP ports, MAC) are runtime programmable, supporting static or DHCP-assigned IP. Includes ARP for multi-access networks, ICMP ping for connectivity tests, and IEEE 802.1Q VLAN tagging. Supports up to 32 transmit and 32 receive streaming interfaces (channels), each independently configurable for IP, port, multicast address, and unicast/multicast mode. Integrates easily in SoC designs via AXI4-Stream, Avalon-ST, AHB, AXI, Avalon-MM, or Wishbone interfaces, with data exchange via streaming ports or memory-mapped registers. Ideal for real-time networking, video streaming, and industrial applications requiring low-latency, deterministic UDP/IP communication in FPGA or ASIC designs.

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Implements a UDP/IP hardware protocol stack enabling high-speed LAN or point-to-point communication and media streaming up to 50 Gbps, even in processor-less SoC designs. Offloads the host CPU from UDP/IP encapsulation. All network parameters (IP addresses, UDP ports, MAC) are runtime programmable, supporting static or DHCP-assigned IP. Includes ARP for multi-access networks, ICMP ping for connectivity tests, and IEEE 802.1Q VLAN tagging. Supports up to 32 transmit and 32 receive streaming interfaces (channels), each independently configurable for IP, port, multicast address, and unicast/multicast mode. Integrates easily in SoC designs via AXI4-Stream, Avalon-ST, AHB, AXI, Avalon-MM, or Wishbone interfaces, with data exchange via streaming ports or memory-mapped registers. Ideal for real-time networking, video streaming, and industrial applications requiring low-latency, deterministic UDP/IP communication in FPGA or ASIC designs.

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The AES-XTS encryption IP core implements hardware encryption/decryption for sector-based storage data. It uses the AES block cipher, in compliance with the NIST Advanced Encryption Standard, as a subroutine. The core processes 128 bits per cycle, and is programmable for 128- and 256-bit key lengths. Two architectural versions are available to suit system size and throughput requirements. The High Throughput XTS-X is more compact and can process 128 bits/cycle independent of the key size. The Higher Throughput XTS-X2 can process 256 bits/cycle independent of the key size. Both versions have a 128-bit data path. XTS (XEX-based Tweaked Codebook Mode with Ciphertext Stealing) is a mode of AES that has been specifically designed to encrypt fixed-size data where a possible threat has access to the stored data.

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The SHA-256 encryption IP core is a fully compliant implementation of the Message Digest Algorithm SHA-256. It computes a 256-bit message digest for messages of up to (2^64 – 1) bits. Developed for easy reuse in ASIC and FPGA applications, the SHA-256 is available optimized for several technologies with competitive utilization and performance characteristics. Support for AMBA bus interfaces and integration with an external DMA are available as options "

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