partner-offering-banner.png

Creonic GmbH

About Creonic GmbH

Program Level

Select

Certified Engineers

10

Languages

English, German, Spanish

Creonic is the ISO 9001:2015 certified leader in ready-for-use IP cores, offering a rich services and product portfolio for wired, wireless, fiber, and free-space optical communications. Covering essential digital signal processing algorithms such as forward error correction, modulation, equalization, and demodulation, as a preeminent provider, our solutions support industry standards like 3GPP 5G, DVB-S2X, DVB-RCS2, CCSDS, and Wi-Fi.

Designed for ASIC and FPGA technologies, Creonic’s products meet the highest benchmarks of quality and performance. Trusted by dozens of customers worldwide, from innovative start-ups to global corporations, our IP cores power communications devices and chipsets, satellites, and NewSpace ventures, enabling unparalleled reliability and success in advanced communication systems.

Headquarters: Bahnhofstraße 26-28, Kaiserslautern, Rheinland-Pfalz, 67655, Germany

View Creonic GmbH's Website Right arrow Right arrow

Offering Type

offering type links Design Services
offering type links Intellectual Property (IP)

Offerings

The Creonic CCSDS AR4JA LDPC IP support the LDPC coding schemes as defined by the CCSDS standard.

View Detail Right arrow Right arrow

The outstanding performance of the DVB-RCS turbo codes makes it the ideal candidate for further applications where high spectral efficiency is key for lowering costs.

View Detail Right arrow Right arrow

The Creonic DVB-S2X Wideband demodulator is a low-complexity high-performance solution that allows for symbol rates of up to 500 MSymb/s on state-of-the-art FPGAs.

View Detail Right arrow Right arrow

The Creonic CCSDS SCCC Turbo IP core the ideal fit for further applications where high throughput and high spectral efficiency is key for operation.

View Detail Right arrow Right arrow

The Creonic WiGig LDPC decoder is designed in particular to deliver highest throughputs in the multi-gigabit domain with a small footprint.

View Detail Right arrow Right arrow

The outstanding error correction performance of the DVB-RCS2 turbo decoder makes it the ideal candidate for further applications where high spectral efficiency is key for lowering costs.

View Detail Right arrow Right arrow

The Creonic CCSDS high performance wideband demodulator performs all tasks of an inner receiver.

View Detail Right arrow Right arrow

The Creonic CCSDS high performance modulator performs all tasks of an inner transmitter.

View Detail Right arrow Right arrow

The Creonic Ultrafast BCH Decoder is capable of processing an entire BCH codeword per clock cycle in a pipelined way. Therefore, it achieves outstanding data rates.

View Detail Right arrow Right arrow

The Creonic DVB-RCS2 Multi-Carrier Receiver IP core supports multiple frequency time domain multiple access (MF-TDMA), performs all tasks of a DVB-RCS2 receiver including carrier separation, baseband conversion, demodulation, and turbo decoding.

View Detail Right arrow Right arrow

The Creonic AWGN Channel IP core is a noise generator capable of processing up to a maximum of 512 symbols in parallel.

View Detail Right arrow Right arrow

The Creonic DVB-S2X wideband modulator is a low-complexity high-performance solution that allows for symbol rates of up to 500 MSymb/s (4 Gbit/s for 256-APSK) on state-of-the-art FPGAs.

View Detail Right arrow Right arrow

The Creonic DVB-S2X demodulator is a low-complexity high-performance solution that allows for symbol rates of up to 100 MSymb/s on state-of-the-art FPGAs and performs all tasks of an inner receiver.

View Detail Right arrow Right arrow

The Creonic CCSDS LDPC IP cores support the LDPC coding scheme as defined by the CCSDS standard.

View Detail Right arrow Right arrow

The Creonic DVB-S2X high performance multi-carrier demodulator performs all tasks of an inner receiver while processing up to 36 carriers in parallel.

View Detail Right arrow Right arrow

The Creonic Polar Encoder IP core is a scalable solution featuring code-rate flexibility, high throughput and very low latency on state-of-the-art FPGAs.

View Detail Right arrow Right arrow

The Creonic NCR Processor IP core has two main functionalities: NCR tracker and NCR local clock

View Detail Right arrow Right arrow

Creonic’s LTE/LTE-A IP core is an advanced, customer proven implementation of the standardized 3GPP turbo code.

View Detail Right arrow Right arrow

The Creonic DVB-S2X decoder is a silicon-proven, scalable solution that allows for symbol rates of up to 100 MSymbols/s on state-of-the-art FPGAs.

View Detail Right arrow Right arrow

The IP core performs all tasks of the inner transmitter and complements the Creonic DVB-RCS2 receiver solutions.

View Detail Right arrow Right arrow

The Creonic IEEE 802.11 LDPC decoder is a high performance implementation for WLAN and further applications and supports all LDPC codes as defined by the standard.

View Detail Right arrow Right arrow

The Creonic DVB-GSE decapsulator performs the decapsulation of BBFRAMEs, containing one or more GSE packets.

View Detail Right arrow Right arrow

The Creonic DVB-C2 IP core integrates the forward error correction as defined by the standard (including LDPC and BCH decoder).

View Detail Right arrow Right arrow

The IP was developed to allow the performance evaluation of a low-earth orbit (LEO) digital communication system.

View Detail Right arrow Right arrow

The Creonic MMSE detector IP core offers high throughputs even on low-cost FPGAs

View Detail Right arrow Right arrow

The Creonic IEEE 802.11 LDPC decoder is a high performance implementation for WLAN and further applications and supports all LDPC codes as defined by the standard.

View Detail Right arrow Right arrow

The Creonic Fast Fourier Transform IP core implements the Decimation in Frequency - Fast Fourier Transform based on the Cooley-Tukey algorithm.

View Detail Right arrow Right arrow

The Creonic DVB-S2X modulator is a low-complexity high-performance solution that allows for symbol rates of up to 250 MSymb/s (2 Gbit/s for 256-APSK) on state-of-the-art FPGAs.

View Detail Right arrow Right arrow

The Creonic IP cores are the ideal solution for throughputs beyond 10 Gbit/s for FPGA devices and throughputs of up to 100 Gbit/s on state-of-the-art ASIC technologies.

View Detail Right arrow Right arrow

The CCSDS 231.0 LDPC IP core supports the LDPC coding schemes and is an ideal fit for further applications with highest demands on forward error correction.

View Detail Right arrow Right arrow

The Creonic DVB-S2 high performance demodulator IP core performs all tasks of an inner receiver. Its output perfectly fits the DVB-S2 forward error correction IP core from Creonic that implements LDPC and BCH decoding.

View Detail Right arrow Right arrow

The Creonic DOCSIS 3.1 LDPC decoder IP cores are a complete solution for the downstream forward error correction, i.e. PLC decoder, NCP decoder and data decoder are included.

View Detail Right arrow Right arrow

The Creonic ITU 25G PON LDPC Encoder and Decoder support the default LDPC (17280, 14592) coding scheme, as well as the optional LDPC (17152, 14592) scheme. The

View Detail Right arrow Right arrow

The Creonic GMR Decoder IP core supports the PNB2 burst packets that were added in GMR Release 2 (GMPRS-1) and use LDPC codes for the first time.

View Detail Right arrow Right arrow

The Creonic IEEE 802.15.3c LDPC Decoder IP supports all LDPC codes with a codeword size of 672 bits as defined by the standard.

View Detail Right arrow Right arrow

The Creonic SDA OCT V3.0 Encoder handles the construction of Over-The-Air (OTA) frames as indicated in the standard, a preamble followed by a header and payload data, with both fields being protected by cyclic redundancy check (CRC) and forward error correction (FEC).

View Detail Right arrow Right arrow

Creonic’s 5G LDPC Decoder and Encoder IP cores provide a perfect solution for this new LDPC structure with high level of flexibility while maintaining high throughput and low latency as required by the standard.

View Detail Right arrow Right arrow

The Creonic DVB-S2 LDPC / BCH Decoder and Encoder IP cores perform forward error correction as defined within the standard.

View Detail Right arrow Right arrow

The Creonic DVB-S2X wideband decoder is a silicon-proven, scalable solution that allows for symbol rates of up to 500 Msymb/s on state-of-the-art FPGAs.

View Detail Right arrow Right arrow

The Creonic Wideband Digital Down Converter (DDC) digitally converts the input signal at IF frequency down to baseband by multiplying input samples with sine/cosine waves generated by numerical controlled oscillators (NCO).

View Detail Right arrow Right arrow

The solution from Creonic for data rates of up to 1 Gbit/s offers outstanding efficiency in terms of implementation complexity.

View Detail Right arrow Right arrow