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Missing Link Electronics

About Missing Link Electronics

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Certified Engineers

13

Languages

English, German, Mandarin Chinese

Missing Link Electronics (MLE) is a Silicon Valley-based technology company with offices in Germany. We have been enabling key innovators in the automotive, industrial, test and measurement markets. MLE's mission is to develop and market technology solutions for Embedded Systems Realization via pre-validated IP and expert application support, and to combine off-the-shelf FPGA devices with Open-Source software for dependable, configurable embedded system platforms. MLE's solutions for Altera comprise of mixed-signal FPGA technology, a direct and single-chip integration of analog I/Os, such as analog-to-digital converter (ADC) and digital-to-analog converter (DAC) into an Altera FPGA. MLE supports Altera FPGA customers to realize video and imaging processing systems, such as wireless transmitters for 3G-SDI full-HD video streaming. MLE also actively contributes to the Nios-II ecosystem.

Headquarters: 2880 Zanker Road, Suite 203, San Jose, California, 95134, United States

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Offering Type

offering type links Boards / SOMs / Dev Kits
offering type links Design Services
offering type links Intellectual Property (IP)

Offerings

TCP/IP full accelerator for 100G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width pipelined all-RTL implementation for ultra-low latency. 

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TCP/IP Full Accelerator for 40G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width pipelined all-RTL implementation for ultra-low latency.

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UDP/IP Full Accelerator for 100G UDP/IP connections. Including UDP, IP, MAC Layer. Pipelined all-RTL implementation for ultra-low Latency.

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TCP/IP Full Accelerator for 10G/25G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width pipelined all-RTL implementation for ultra-low latency. 

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NVMe is a key protocol for connecting SSDs to high-performance systems, leveraging PCIe for faster read/write speeds. MLE's NVMe Streamer 5.0 is a Full Accelerator NVMe host subsystem optimized for Altera Agilex 7 I-Series with R-Tiles FPGAs and Agilex 5 FPGAs. Running entirely in Programmable Logic, it bypasses the Processing System for maximum performance, using Transceivers and PCIe Hard IP Cores for seamless PCIe connectivity.

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NVMe is a key protocol for connecting SSDs to high-performance systems, leveraging PCIe for faster read/write speeds. MLE's NVMe Streamer 4.0 is a Full Accelerator NVMe host subsystem optimized for Altera Agilex 7 F-/I-Series with F-Tiles and Agilex 5 FPGAs, built on successful customer projects. Running entirely in Programmable Logic, it bypasses the Processing System for maximum performance, using Transceivers and PCIe Hard IP Cores for seamless PCIe connectivity.

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MLE offers FPGA design services for Altera® FPGAs, which give a wide variety of configurable embedded SRAM, high-speed transceivers, high-speed I/Os, logic blocks, and routing. Built-in intellectual property (IP) combined with outstanding software tools lower FPGA development time, power, and cost.

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Openness has greatly benefited other industries like automotive, aerospace, banking, datacenters, and finally OT: No vendor lock-in, higher flexibility and better long-term-availability. Cost reduction for Overall Equipment Effectiveness (OEE). Meets today’s cyber security requirements. Opens-up use of AI.

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Applications: Autonomous Vehicle Path Record & Replay. Automotive / Medical / Industrial Test Equipment. Broadcast Recording. High-speed Radar / Lidar / Camera Data Acquisition & Storage. Network Telemetry and Analytics. Very Deep Network Packet Capture of Ethernet or IPv4 or TCP/UDP Data.

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The 10G Ethernet MAC IP Core from Fraunhofer Heinrich Hertz Institute is a low latency Ethernet Media Access Controller (MAC) according to IEEE802.3 -2008 specification. The IP Core was specifically designed to have the lowest possible latency, and to be as resource efficient as possible at the same time.

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MLE’s Mixed-Signal FPGA technology further broadens the application space from pure digital protocols to so-called “amplitude-modulated” protocols which require plenty of configurable analog I/Os embedded inside proven off-the-shelf FPGA devices.

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The MLE 40G FPGA SmartNIC PCIe Card is a Single-Slot FHHL PCIe SmartNIC integrating an Intel Stratix 10 GX 400 FPGA, 4x SFP for 4x 10 GigE, a FPGA-attached DDR4 DRAM via SO-DIMM and with 50 Watts TDP passive cooling front-to-back. It provides 40 Gbps Source-to-Sink Data Transport, a full accelerator to fully offload the CPU, and cost-efficient, customizable and ready-to-run.

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MLE 50G TCP/IP is a stand-alone TCP/IP Stack Full Accelerator Subsystem allowing 50Gbps communication at full line rate and low latency. It includes TCP, IP, MAC Layer, supports 128-bit wide full duplex data width, and pipelines all-RTL implementation for high throughput and ultra low Latency.

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UDP/IP Full Accelerator for 50G UDP/IP connections. Including UDP, IP, MAC Layer. Pipelined all-RTL implementation for ultra low Latency.

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UDP/IP Full Accelerator for 10G/25G UDP/IP connections. Including UDP, IP, MAC Layer. Pipelined all-RTL implementation for ultra low Latency.

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UDP/IP Full Accelerator for 40G UDP/IP connections. Including UDP, IP, MAC Layer. Pipelined all-RTL implementation for ultra low Latency.

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