partner-offering-banner.png

Altera

About Altera

Program Level

Certified Engineers

Languages

English, French, German, Hindi, Japanese, Mandarin Chinese, Spanish, Urdu

Altera, provides leadership programmable solutions that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation.

Our innovation of programmable logic started in 1983 in Silicon Valley. In 1984, Altera unveiled the world’s first programmable logic device capable of being programmed, erased, and reprogrammed altering the future of innovation.

Headquarters: 101 Innovation Drive, San Jose, California, 95134, United States

View Altera's Website Right arrow Right arrow

Offering Type

offering type links Acceleration / AI / Cloud
offering type links Boards / SOMs / Dev Kits
offering type links EDA Tools / IDE
offering type links Education / Training
offering type links Intellectual Property (IP)
offering type links Software / OS / RTOS

Offerings

DK-A3W135BM16AEA: Agilex™ 3 FPGA and SoC C-Series Development Kit is a compact, power-efficient platform for embedded and edge applications, featuring DisplayPort 1.4, dual MIPI interfaces, and Raspberry Pi HAT expansion.

View Detail Right arrow Right arrow

MK-A5E065BB32AEA: Agilex™ 5 FPGA and SoC E-Series 065B Modular Development Kit delivers a complete prototyping and reference platform design environment that includes both hardware and software. It is a general-purpose evaluation board in PCIe form factor with HPS hardware features enabling you to develop industrial, video, and other embedded and edge applications.​

View Detail Right arrow Right arrow

[DISCONTINUED] DK-DEV-2ARF-FA-A: The Agilex™ 9 Direct RF-Series AGRW027 Development Kit provides a powerful platform for developing and testing high-speed RF applications. Supports direct RF sampling and advanced signal processing capabilities. This kit is ideal for engineers building next-generation RF systems with high bandwidth and precision timing requirements.

View Detail Right arrow Right arrow

DK-DEV-AGM039EA: The Agilex™ 7 FPGA M-Series Development Kit - HBM2e Edition is a high-performance platform for high memory bandwidth applications, featuring Agilex M-Series FPGA with up to 820 GB/s memory and PCIe Gen5 support.

View Detail Right arrow Right arrow

DK-DEV-2ARF-FA-B: The Agilex™ 9 Direct RF-Series AGRW027 Development Kit provides a powerful platform for developing and testing high-speed RF applications. Supports direct RF sampling and advanced signal processing capabilities. This kit is ideal for engineers building next-generation RF systems with high bandwidth and precision timing requirements.

View Detail Right arrow Right arrow

DK-DEV-AGF023FA: The Agilex™ 7 FPGA F-Series Development Kit (2x F-Tile) (AGF023) offers a scalable platform for evaluating mid- to high-end Agilex FPGAs, featuring PCIe Gen4 and high-speed memory interfaces.

View Detail Right arrow Right arrow

DK-A5E065BB32AEA: Agilex® 5 FPGA and SoC E-Series Premium Development Kit delivers a complete prototyping and reference platform design environment that includes both hardware and software for your Agilex® 5 FPGA E-Series development needs. ​

View Detail Right arrow Right arrow

EK-10M08E144: The MAX® 10 FPGA 10M08 Evaluation Kit (POWER SOL'N 1) provides a low-cost, entry-level platform for evaluating the MAX 10 FPGA family, featuring integrated flash and ADCs.

View Detail Right arrow Right arrow

DK-SI-1STX-E-A: The Stratix® 10 TX Signal Integrity Development Kit enables 58 Gbps PAM4 transceiver evaluation with SMA and QSFP-DD connectivity.

View Detail Right arrow Right arrow

DK-SI-1SGX-H-A: The Stratix® 10 GX Signal Integrity Development Kit (H-TILE) is designed for high-speed transceiver and signal integrity testing, featuring 28 Gbps and 56 Gbps transceiver support and advanced measurement capabilities.

View Detail Right arrow Right arrow

DK-SOC-1SSX-H-D: The Stratix® 10 SX SoC Development Kit accelerates advanced SoC development utilizing high-bandwidth memory and versatile I/O

View Detail Right arrow Right arrow

DK-A5E065AB32AEA: Agilex™ 5 FPGA and SoC E-Series Premium Development Kit delivers a complete prototyping and reference platform design environment that includes both hardware and software for your Agilex™ 5 FPGA E-Series development needs. ​

View Detail Right arrow Right arrow

DK-DEV-5SGXEA7N: The Stratix® V GX FPGA Development Kit is a flexible platform for high-performance FPGA development, featuring Stratix V GX FPGAs and support for PCIe and high-speed serial interfaces.

View Detail Right arrow Right arrow

DK-DEV-4ARF-FA-A: A premium development platform for engineers building direct-RF FPGA systems that combine embedded data conversion, high-speed serial connectivity, and large-scale digital signal processing

View Detail Right arrow Right arrow

DK-100G-5SGXEA7N: The Stratix® V GX 100G Development Kit is a high-bandwidth platform for 100G Ethernet applications, featuring a Stratix V GX FPGA and integrated 100G MAC/PHY reference designs.

View Detail Right arrow Right arrow

[DISCONTINUED] DK-DEV-5CEA7N: The Cyclone® V E FPGA Development Kit offers a comprehensive general purpose development platform for Cyclone V FPGAs, and features an abundance of interactive options.

View Detail Right arrow Right arrow

DK-SOC-10AS066S-E: The Arria® 10 SX SoC Development Kit provides a comprehensive platform for developing advanced embedded, networking, and signal processing applications

View Detail Right arrow Right arrow

DK-DEV-5M570ZN: The MAX® V CPLD Development Kit provides a low-cost, flexible platform for evaluating MAX V CPLDs, featuring a compact design and abundant connectivity options for rapid prototyping.

View Detail Right arrow Right arrow

DK-SI-5SGXEA7N: The Stratix® V GX Transceiver SI Development Kit offers a complete platform for signal integrity testing, featuring Stratix V GX FPGAs and support for up to 12.5 Gbps transceiver data rates.

View Detail Right arrow Right arrow

DK-SI-AGI027FD: The Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit is a signal integrity-focused platform for evaluating high-speed transceivers on Agilex I-Series FPGAs, featuring SMA connectors, MXMP and QSFP-DD ports for direct measurement.

View Detail Right arrow Right arrow

[DISCONTINUED] DK-A3Y135BM16AEA: The Agilex® 3 FPGA C-Series Development Kit is a compact, power-efficient platform for embedded and edge applications, featuring DisplayPort 1.4, dual MIPI interfaces, and Raspberry Pi HAT expansion.

View Detail Right arrow Right arrow

DK-SI-1SGX-L-A: The Stratix® 10 GX FPGA Signal Integrity Development Kit (L-TILE) is designed for high-speed transceiver and signal integrity testing, featuring 28 Gbps and 56 Gbps transceiver support and advanced measurement capabilities.

View Detail Right arrow Right arrow

DK-SI-10AX115S-A: The Arria® 10 GX Transceiver Signal Integrity Development Kit is optimized for high-speed serial link evaluation, featuring Arria 10 GX FPGA and comprehensive transceiver access for signal integrity testing.

View Detail Right arrow Right arrow

DK-DEV-5CGTD9N-B: The Cyclone® V GT FPGA Development Kit provides a robust platform for evaluating high-speed transceiver capabilities of the Cyclone V GT FPGA, featuring PCIe Gen2 x4 and DDR3 support.

View Detail Right arrow Right arrow

DK-DEV-5CSXC6N-B: The Cyclone® V SX SoC Development Kit offers a complete SoC FPGA platform with integrated ARM Cortex-A9 processors, ideal for embedded system development and hardware/software co-design.

View Detail Right arrow Right arrow

DK-DEV-10CX220-B: The Cyclone® 10 GX Development Kit is a cost-effective platform for transceiver-based applications, featuring high-speed I/O and robust memory support.

View Detail Right arrow Right arrow

EK-10CL025U256: The Cyclone® 10 LP Evaluation Kit is a low-cost, low-power platform ideal for entry-level FPGA development and education.

View Detail Right arrow Right arrow

[DISCONTINUED] DK-SI-AGI027FC: The Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit is a signal integrity-focused platform for evaluating high-speed transceivers on Agilex I-Series FPGAs, featuring SMA connectors, MXMP and QSFP-DD ports for direct measurement.

View Detail Right arrow Right arrow

MK-A5E065AB32AEA: Agilex™ 5 FPGA and SoC E-Series 065A Modular Development Kit delivers a complete prototyping and reference platform design environment that includes both hardware and software. It is a general-purpose evaluation board in PCIe form factor with HPS hardware features enabling you to develop industrial, video, and other embedded and edge applications.​

View Detail Right arrow Right arrow

[PREVIEW] DK-DEV-10AX115S-B: The Arria® 10 GX FPGA Development Kit is a high-performance platform for prototyping FPGA designs, featuring Arria 10 GX FPGA with high-speed transceivers and PCIe Gen3 support.

View Detail Right arrow Right arrow

[DISCONTINUED] DK-DEV-10AX115S-A: The Arria® 10 GX FPGA Development Kit is a high-performance platform for prototyping FPGA designs, featuring Arria 10 GX FPGA with high-speed transceivers and PCIe Gen3 support.

View Detail Right arrow Right arrow

DK-DEV-10M08E144-B: The MAX® 10 FPGA 10M08 Evaluation Kit (POWER SOL'N 2) provides a low-cost, entry-level platform for evaluating the MAX 10 FPGA family, featuring integrated flash and ADCs.

View Detail Right arrow Right arrow

DK-DEV-10M50F484-B: The MAX® 10 FPGA 10M50 Evaluation Kit is a compact, yet feature-rich platform for prototyping, offering a variety of connectivity options including HDMI

View Detail Right arrow Right arrow

DK-DEV-10M50-C: The MAX® 10 FPGA Development Kit is a versatile platform for system-level FPGA development, featuring embedded flash and dual ADCs.

View Detail Right arrow Right arrow

The Stratix® V GS DSP Development Kit provides a complete design environment that includes all the hardware and software you need to begin developing DSP-intensive FPGA designs in a PCIe form factor

View Detail Right arrow Right arrow

Mobile Industry Processor Interface (MIPI) D-PHY is supported on Agilex™ 5 and Agilex™ 3 FPGAs allowing transmission and reception of data through PHY-protocol interface (PPI) to connect with camera serial interface (CSI) and display serial interface (DSI) applications.

View Detail Right arrow Right arrow

The 10GBASE-R PHY FPGA Intellectual Property (IP) core can be used with either Altera FPGA IP for 10G Ethernet MAC or with a customer-developed Ethernet MAC via a standard XGMII interface running at 156.25 Mbps.

View Detail Right arrow Right arrow

The XAUI PHY IFPGA IP core allows you to easily build systems with a very high throughput 10G Ethernet connection. This XAUI PHY along with a 10GbE media access control (MAC) IP core enables an Altera FPGA to interface to a 10GbE network through a variety of external devices, including a 10GbE PHY device or optical transceiver module. You can implement the XAUI PHY in hard silicon in Intel's 65 nm and 40 nm FPGAs with serial transceivers faster than 3 Gbps. The PHY management functions are implemented in soft IP. In Intel 20 nm and beyond FPGA families, a XAUI PHY can be implemented in soft IP.

View Detail Right arrow Right arrow

LVDS Tunneling Protocol and Interface (LTPI) is a soft IP introduced in the DC-SCM 2.0 specification to facilitate the tunneling of low-speed signals between the host platform module (HPM) and secure control module (SCM) through the low-voltage differential signaling (LVDS) interfaces.

View Detail Right arrow Right arrow

The CIC FPGA IP core offers computationally efficient cores for extracting baseband signals.

View Detail Right arrow Right arrow

The FIR II IP cores provide a fully-integrated finite impulse response (FIR) filter function optimized for use with Altera FPGA devices.

View Detail Right arrow Right arrow

Numerically Controlled Oscillator IP for discrete-time, discrete-valued representation of a sinusoidal waveform.

View Detail Right arrow Right arrow

The Reed Solomon II IP offers a fully parameterizable Reed Solomon encoder and decoder.

View Detail Right arrow Right arrow

The Fast Fourier transform (FFT) FPGA intellectual property (IP) core is a high-performance, highly parameterizable FFT processor.

View Detail Right arrow Right arrow

The Viterbi Intel FPGA IP core generates high-performance, soft-decision Viterbi intellectual property (IP) functions that implement a wide range of standard Viterbi decoders.

View Detail Right arrow Right arrow

A complete 10/100/1000 Mbps Ethernet IP with flexible IP options including MAC only, PCS only, MAC + PCS, MAC + PCS + PMA, PCS + PMA.

View Detail Right arrow Right arrow

The Backplane Ethernet 10GBASE-KR PHY Altera FPGA Intellectual Property (IP) core is a transceiver PHY that allows you to instantiate the hard standard physical coding sublayer (PCS), the higher performance hard 10G PCS, and the hard physical medium attachment (PMA) for a single Backplane Ethernet channel.

View Detail Right arrow Right arrow

The 10GBASE-R PHY FPGA Intellectual Property (IP) core can be used with either Altera FPGA IP for 10G Ethernet MAC or with a customer-developed Ethernet MAC via a standard XGMII interface running at 156.25 Mbps.

View Detail Right arrow Right arrow

The 1G/10G Ethernet PHY Altera FPGA Intellectual Property (IP) core supports functionality of both the standard physical coding sublayer (PCS) and the higher data rate 10G PCS with an appropriate physical medium attachment (PMA). 

View Detail Right arrow Right arrow

The Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates from 10M to 10GbE in accordance with the IEEE 802.3 Ethernet Standard without any design regeneration or device reconfiguration.

View Detail Right arrow Right arrow

The Agilex 7 FPGA F-Tile IP core implements Ethernet at data rates of 10 Gbps, 25 Gbps, 40 Gbps, 50 Gbps, 100 Gbps, 200 Gbps and 400 Gbps. The user can choose a media access control (MAC) and a physical coding sublayer (PCS) variation, a PCS-only variation, a Flexible Ethernet (FlexE) variation, or an Optical Transport Network (OTN) variation.

View Detail Right arrow Right arrow

The Agilex 7 and Stratix 10 FPGA E-Tile incorporates a configurable, hardened Ethernet protocol stack compatible with the IEEE 802.3 High-Speed Ethernet Standard and the 25G and 50G Ethernet Specification, Draft 1.6 from the 25G Ethernet Consortium. The Intellectual Property (IP) core provides access to this hard IP at data rates of 10 Gbps, 25 Gbps, and 100 Gbps.

View Detail Right arrow Right arrow

The Low Latency Ethernet 10G MAC FPGA IP core offers low round-trip latency and efficient resource footprint. This IP core offers programmability of various features listed. It can be used in conjunction with the Multi-Rate PHY FPGA IP core to support the range of 10M/100M/1G to 10G data rates.

View Detail Right arrow Right arrow

The 25G Ethernet IP core implements the 25G and 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium. This IP core optionally includes unidirectional transport and Reed-Solomon Forward Error Correction (FEC) for support of direct attach copper (DAC) cable.

View Detail Right arrow Right arrow

The 40G Ethernet MAC and PHY FPGA IP core offers IEEE 802.3ba-2010. 40 Gbps Ethernet is an industry standard and is compliant for media access control (MAC) and PHY (PCS+PMA) functions. It enables an FPGA to interface to another device over a copper or optical transceiver module.

View Detail Right arrow Right arrow

The 50G Ethernet FPGA IP core implements the 25G & 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium and the IEEE 802.3by 25Gb Ethernet draft. The IP core provides standard media access control (MAC), physical coding sublayer (PCS), and PMA functions. The PHY comprises the PCS and PMA.

View Detail Right arrow Right arrow

The Stratix 10 H-Tile Ethernet Hard IP core is available with a 100GBASE-R4 Ethernet channel. For the Ethernet data rate, you can choose a media access control (MAC) + physical coding sublayer (PCS) variation or a PCS-only variation.

View Detail Right arrow Right arrow

Altera offers ultimate flexibility, scalability, and configurability with the Low Latency 100G Ethernet FPGA IP core targeted to network infrastructure and data centers. The Low Latency 100G Ethernet FPGA IP core is compliant with the IEEE 802.3ba-2010 Standard. It includes a media access control (MAC), PHY, physical coding sublayer (PCS), physical medium attachment (PMA), and an optional forward error correction (FEC) block.

View Detail Right arrow Right arrow

Interlaken is an interconnect protocol for high-speed, channelized chip-to-chip interface in networking applications. It is optimized for high-bandwidth chip-to-chip packet transfers at rates from 10 Gbps to 600 Gbps and beyond.

View Detail Right arrow Right arrow

The Serial Lite FPGA IP core is a simple, low-latency, scalable protocol for high-bandwidth serial data transfer applications. It is suitable for high-bandwidth data communication for chip-to-chip, board-to-board, and backplane applications. The core incorporates a media access control (MAC), physical coding sublayer (PCS), and physical media attachment (PMA) block.

View Detail Right arrow Right arrow

Altera CPRI FPGA IP delivers a high-performance, standards-compliant implementation of the CPRI Specification V7.0, enabling reliable, high-speed communication between Radio Equipment Controllers (RECs) and Remote Radio Equipment (REs). Fully configurable as either REC or RE, the IP simplifies integration in remote radio network applications and accelerates deployment of robust, low-latency fronthaul links.

View Detail Right arrow Right arrow

Altera eCPRI FPGA IP implements the eCPRI 2.0 specification, providing a high-performance front-haul interface for next-generation radio base stations. It enables seamless, low-latency connectivity between eCPRI Radio Equipment Control (eREC) and Radio Equipment (eRE) over front-haul transport networks, accelerating deployment of scalable, flexible 5G infrastructure.

View Detail Right arrow Right arrow

Altera JESD204 IP is a high-performance, JEDEC-compliant interface solution designed to simplify and accelerate the integration of high-speed data converters with digital processing systems. Supporting data rates up to 32.44 Gbps, it efficiently manages the physical, data link, and transport layers while offering pre-verified design examples and intuitive configuration, significantly reducing development time. Its robust clock synchronization and interoperability features ensure reliable, standards-based performance across demanding applications.

View Detail Right arrow Right arrow

DDR4 and DDR5 offer higher bandwidth and improved performance over previous generations, with DDR5 providing further enhancements in speed and power efficiency. LPDDR4 and LPDDR5 are optimized for low power consumption, making them ideal for embedded applications, with LPDDR5 offering even faster data rates and improved energy management. When integrated with Altera FPGAs these memory technologies enable faster data processing and more efficient power usage for a wide range of applications including networking, cloud and edge.

View Detail Right arrow Right arrow

Nios® V processors are the next generation of soft processor IPs, designed to bring the power and flexibility of the open-source RISC-V Architecture to FPGA environments. By leveraging the RISC-V instruction set architecture (ISA), the Nios V processors offer scalable solutions that enable a spectrum of applications ranging from simple embedded systems to complex, high-performance applications.

View Detail Right arrow Right arrow

CXL IP is designed to provide the added memory bandwidth and capacity, and acceleration needed for a wide range of data-intensive workloads.

View Detail Right arrow Right arrow

The MACsec FPGA IP core is a fully configurable soft IP that implements the IEEE Media Access Control Security standard as defined in 802.1AE (2018). MACsec provides data confidentiality and integrity for the Ethernet protocol and is commonly used to secure network traffic in a variety of different applications.

This IP core makes use of the Symmetric Cryptographic Accelerator (SCA) Hard IP, which is available in select Agilex 7 F-series and I-series devices. With the SCA, Altera's MACsec IP core can achieve 100 Gbps full-duplex line rates. Note that the SCA can also be used as a stand alone cryptographic accelerator.

View Detail Right arrow Right arrow

The Symmetric Cryptographic Accelerator Hard IP is a 200 Gbps hard IP core implementing AES or SM4 encryption and decryption. Typically, the AES and SM4 standards are used to protect the confidentiality of network data in 5G, data center, medical, test and video, but can be used to secure any high-speed data in transit. In fact, this hard IP is called by Altera's MACsec IP solution as a hardened accelerator, but can be used in any application requiring these encryption standards. In addition, the XTS profile can be used in data storage applications.

View Detail Right arrow Right arrow

F-Tile is an FPGA companion tile that supports PCI Express* configurations up to PCIe 4.0 x16 in Endpoint (EP), Root Port (RP) and Transaction Layer (TL) Bypass modes. PCIe 3.0 and 4.0 configurations are natively supported.

View Detail Right arrow Right arrow

GTS PCIe Hard IP is a full featured protocol stack with AXI4-Stream user interface available on Agilex™ 5 and Agilex™ 3 FPGAs.

View Detail Right arrow Right arrow

L/H-Tile are each an FPGA companion tile that supports PCI Express* configurations up to PCIe 3.0 x16 in Endpoint (EP) and Root Port (RP) modes.

View Detail Right arrow Right arrow

Accelerate designs with Multichannel DMA for PCIe IP – fast and efficient data movement, flexible features, and Linux driver support.

View Detail Right arrow Right arrow

P-Tile is an FPGA companion tile that supports PCI Express* configurations up to PCIe 4.0 x16 in Endpoint (EP), Root Port (RP) and Transaction Layer (TL) Bypass modes. PCIe 3.0 and 4.0 configurations are natively supported.

View Detail Right arrow Right arrow

Configurable PCIe 3.0/2.0 hard IP on Arria® 10 & Cyclone® 10 GX FPGAs with Root Port/Endpoint, Avalon-ST, Avalon-MM, and SR-IOV and DMA options.

View Detail Right arrow Right arrow

R-Tile is an FPGA companion tile that supports PCI Express* configurations up to PCIe 5.0 x16 in Endpoint (EP), Root Port (RP) and Transaction Layer (TL) Bypass modes. PCIe 3.0, 4.0, and 5.0 configurations are natively supported.

View Detail Right arrow Right arrow

The Scalable Switch IP for PCIe is a fully configurable switch that implements one fully configurable upstream port and connectivity for up to 96 downstream ports.

View Detail Right arrow Right arrow

HBM2E is a high-performance memory IP that offers a combination of high memory bandwidth, low power consumption, low latency, and small form factor for Agilex™ 7 FPGA M-Series devices. HBM2E memory is well-suited for various high-performance computing applications.

View Detail Right arrow Right arrow

The Altera FPGA Video and Vision Processing Suite is a collection of next-generation Altera intellectual property (IP) functions that you can use to facilitate the development of custom video and image processing designs.

View Detail Right arrow Right arrow

The Tone Mapping Operator (TMO) FPGA IP corrects poorly exposed images and video to reveal invisible details.

View Detail Right arrow Right arrow

The 3D Look-Up Table (LUT) Altera® FPGA IP, part of the Video and Vision Processing (VVP) Suite, delivers a high-performance, resource-efficient solution for video color space conversion, dynamic range adjustment, chroma keying, and artistic effect generation, enabling superior image quality in broadcast and professional video applications.

View Detail Right arrow Right arrow

The HDMI Altera® FPGA IP core delivers high-performance, standards-compliant support for the latest HDMI specifications, enabling seamless transmission of high-definition audio and video over a single interface. It provides a robust and flexible solution for integrating next-generation video display connectivity into Altera FPGA designs.

View Detail Right arrow Right arrow

The Altera SDI II FPGA IP core enables high-performance serial digital interface (SDI) transmission and reception across SD, HD, and 3G to 12G video rates.

View Detail Right arrow Right arrow

The Altera Warp FPGA IP core, part of the Video and Vision Processing (VVP) Suite, delivers a high-performance solution for applying geometric corrections and non-linear transformations to real-time video streams.

View Detail Right arrow Right arrow

The GTS Ethernet Hard IP (EHIP) allows fast, flexible, and high-performance Ethernet implementation with minimal FPGA resource utilization. The EHIP includes a configurable, hardened protocol stack for Ethernet compatible with the IEEE 802.3-2018 Standard and the 25G/50G Ethernet Specification from the 25 Gigabit Ethernet Consortium.

View Detail Right arrow Right arrow

DK-DEV-AGI027-RA-B: The Agilex™ 7 FPGA I-Series Development Kit is a high-performance platform for evaluating Agilex I-Series FPGAs, featuring PCIe 5.0, CXL and QSFP-DD connectivity for advanced networking applications.

View Detail Right arrow Right arrow

DK-A5E065BB32AES1: Agilex™ 5 FPGA and SoC E-Series Premium Development Kit (ES) delivers a complete prototyping and reference platform design environment that includes both hardware and software for your Agilex™ 5 FPGA E-Series development needs. ​

View Detail Right arrow Right arrow

DK-SI-AGF014EB: The Agilex 7 FPGA F-Series Transceiver-SoC Development Kit (Rev B) is a high-performance platform for transceiver-rich FPGA and SoC development with advanced connectivity and memory support.

View Detail Right arrow Right arrow

DK-DEV-AGF014EB: The Agilex® 7 FPGA F-Series Development Kit (P-Tile and E-Tile) is a flexible platform for Agilex 7 F-Series FPGA evaluation, featuring PCIe Gen4 and DDR4 support.

View Detail Right arrow Right arrow

Low-density parity-check (LDPC) IP helps transmit and receive messages over noisy channels. This IP implements LDPC codes compliant with the 3rd generation partnership project 5G specification.

View Detail Right arrow Right arrow

Turbo codes assist in forward error correction systems. You can use Turbo codes in other applications that require reliable information transfer over bandwidth- or latency-constrained communication links in the presence of data-corrupting noise.

View Detail Right arrow Right arrow

[DISCONTINUED] DK-SI-AGI027FA: The Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit is a signal integrity-focused platform for evaluating high-speed transceivers on Agilex I-Series FPGAs, featuring SMA connectors, MXMP and QSFP-DD ports for direct measurement.

View Detail Right arrow Right arrow

Altera O-RAN IP delivers a flexible, standards-compliant fronthaul interface for 5G and LTE systems using the 7-2x functional split. Supporting both control and user planes per O-RAN-FH.CUS.0-v03.00, it simplifies DU-RU integration, accelerates development, and ensures interoperability in disaggregated, open RAN architectures.

View Detail Right arrow Right arrow

[DISCONTINUED] MK-A5E065BB32AES1: Agilex™ 5 FPGA and SoC E-Series Modular Dev Kit (ES) delivers a complete prototyping and reference platform design environment that includes both hardware and software. It is a general-purpose evaluation board in PCIe form factor with HPS hardware features enabling you to develop industrial, video, and other embedded and edge applications.​

View Detail Right arrow Right arrow

[DISCONTINUED] DK-DEV-AGF014EA: The Agilex™ 7 FPGA F-Series Development Kit (P-Tile and E-Tile) is a flexible platform for Agilex 7 F-Series FPGA evaluation, featuring PCIe Gen4 and DDR4 support.

View Detail Right arrow Right arrow

[DISCONTINUED] DK-DEV-AGM039FES: The Agilex™ 7 FPGA M-Series Development Kit - HBM2e Edition (ES) is a high-performance platform for high memory bandwidth applications, featuring Agilex M-Series FPGA with up to 820 GB/s memory and PCIe Gen5 support.

View Detail Right arrow Right arrow

[DISCONTINUED] DK-SI-AGF014EA: The Agilex 7 FPGA F-Series Transceiver-SoC Development Kit (Rev A) is a high-performance platform for transceiver-rich FPGA and SoC development with advanced connectivity and memory support.

View Detail Right arrow Right arrow

[DISCONTINUED] DK-DEV-AGI027-RA: The Agilex™ 7 FPGA I-Series Development Kit is a high-performance platform for evaluating Agilex I-Series FPGAs, featuring PCIe Gen4 and QSFP-DD connectivity for advanced networking applications.

View Detail Right arrow Right arrow

DK-SI-AGI040EA: The Agilex™ 7 FPGA I-Series Transceiver Development Kit (6x F-Tile) is a high-speed signal integrity platform for PAM4 transceiver testing, featuring SMA and QSFP-DD connectivity and optimized layout for low-loss signal paths.

View Detail Right arrow Right arrow

[DISCONTINUED] DK-SI-AGI040FES: The Agilex™ 7 FPGA I-Series Transceiver Development Kit (6x F-Tile) (ES) is a high-speed signal integrity platform for PAM4 transceiver testing, featuring SMA and QSFP-DD connectivity and optimized layout for low-loss signal paths.

View Detail Right arrow Right arrow

DK-A5E013BM16AEA: The Agilex® 5 FPGA E-Series 013B Development Kit is a compact, power-efficient platform for embedded and edge applications, featuring DisplayPort 1.4, dual MIPI interfaces, and Raspberry Pi HAT expansion.

View Detail Right arrow Right arrow

DK-DEV-3ARF-FD-A: Agilex™ 9 Direct RF-Series Medium-Band Development Kit. Accelerate RF innovation for applications up to C-band frequencies, with direct sampling, high bandwidth, and precision clocking—all in one integrated development platform.

View Detail Right arrow Right arrow

DK-DEV-1ARF-FA-A: The Agilex™ 9 Direct RF-Series AGRW014 Development Kit provides a powerful platform for developing and testing high-speed RF applications. Supports direct RF sampling and advanced signal processing capabilities. This kit is ideal for engineers building next-generation RF systems with high bandwidth and precision timing requirements.

View Detail Right arrow Right arrow