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TES Electronic Solutions GmbH

About TES Electronic Solutions GmbH

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Languages

English, German

TES Electronic Solutions (TES) is a premier full-spectrum design house and innovative technology provider, specialized in delivering high-complexity embedded systems and silicon-proven IP as a long-standing partner within the Altera ecosystem that empowers customers to accelerate time-to-market while reducing technical risk in demanding FPGA-based projects. Our production-ready Digital IP portfolio for Altera FPGAs is engineered for seamless integration, high customizability, and high performance, providing specialized solutions in Graphics & GUIs with industry-leading 2D, 2.5D, and 3D vector graphics IP cores (D/AVE GPU family) and GUI frameworks, as well as advanced IP cores for high-resolution Video IO and processing, robust stacks for wireless connectivity, and secure hardware accelerators for cryptography. Bridging the gap from initial concept to Ready-for-Market products, our full-cycle design services cover everything from architecture definition and feasibility studies to complex FPGA/ASIC RTL design, hardware-software co-design, and full supply chain management. Our elite team of engineering experts optimizes for power, area, and latency to ensure products outperform the competition through a multidisciplinary approach where FPGA logic, high-speed PCB design, and low-level software work in perfect harmony. Headquartered in Germany with design centers in Stuttgart, Hamburg, Dusseldorf, Offenbach, Berlin, and Munich, TES combines Made in Germany quality with global reach to support customers in the Industrial, Automotive, Avionics, Medical, Test and Measurement, Defense, and Consumer sectors, transforming Altera-based visions into high-performance reality.

Headquarters: Nikolaus-Otto-Strasse 25, Leinfelden-Echterdingen, Baden Wurttemberg, 70771, Germany

Offering Type

Offerings

3D Shader programmable 3D GPU IP core with OpenGL ES 2.0 API (and option for OpenGL SC) under bare metal / RTOS / Linux. Highly configurable concerning performance vs. footprint (1 ShaderUnit with 4 FP32 ALUs up to 4 Shader Units with 128 FP32 ALUs) - all configurations with the same feature set.

FPGA and ASIC design service from concept to complete system, including of software drivers and BSP. From FPGA prototype to ASIC, an inclusive supply chain.

PCB design, including supply chain under ODM model, includes complex high-speed systems, RF systems up to 120GHz, and mixed-signal PCBs.

Highly customizable MIPI-DPI compliant display controller supporting on-the-fly image composition from several input sources (images in memory or AXI4 Stream) with a powerful set of image processing features.

Video input controller capturing an RGB or ITU-R BT.656/BT.601 video input stream to memory with configurable functions, e.g., scaling, color format conversion, clipping, dithering.

Memory -to memory or memory to stream Warping engine for projectors, fish-eye lense correction or Head Up Displays (HUDs).

2.5D fixed-function GPU IP core with advance vector graphics support, highly configurable concerning feature set vs. footprint. Efficient D/AVE HD API and optional OpenVG 1.1 API under bare metal / RTOS / Linux.

2D fixed-function GPU IP core with vector graphics support and optimal feature/footprint balance. Efficient D/AVE 2D API under bare metal / RTOS / Linux.