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FPGA Authority

About FPGA Authority

Program Level

Member

Certified Engineers

2

Languages

English

FPGA Authority is an Altera® certified trainer that provides in-depth, technically detailed instruction covering the complete FPGA and SoC design process. Training spans RTL hardware design, embedded software development and system-level integration, including processor-based SoC platforms and High-Level Synthesis (HLS) workflows. Emerging technologies including AI/ML applications, DSP and algorithm implementation are offered. Courses emphasize architectural trade-offs, dataflow design, performance analysis, and resource utilization, enabling engineers to design efficient, scalable FPGA solutions from specification through implementation. Embedded topics discuss RISC-V architecture, Yocto, Zephyr, Python and software design methodologies. The curriculum includes detailed treatment of HDL coding techniques, synthesis considerations, timing analysis and constraint development, along with comprehensive verification methodologies. Emphasis is on building robust testbenches, simulation and waveform-based debugging, and performing hardware debug using Altera tools. Attention is given to functional verification, corner-case analysis, and root-cause debugging to ensure deterministic, maintainable designs. Courses are designed for beginner to expert level system architects, hardware developers, software designers and verification engineers who require practical, tool-driven expertise to confidently plan, create, verify, and debug production-quality FPGA-based and SoC-based systems.

Headquarters: Kanata, Ontario, Canada

Offering Type

Offerings

This is the advanced course of a two course formal verification progression. It assumes comprehensive knowledge of “Applied Formal Verification” and applies formal methods to the problems that dominate real Altera SoC designs.

This is the foundation course of a two course formal verification progression. It delivers a complete, hands-on grounding in formal methods using SystemVerilog Assertions and the Questa Formal tool flow

This advanced course tackles the unique and technically demanding challenges that arise when an ARM Cortex A9/A53 Hard Processor System must be co-verified alongside custom programmable logic fabric connected through high bandwidth AXI bridge interfaces.

This course is targeted towards Design and Verification engineers who wish to deploy Assertion Based Verification (ABV) within their next project.

This advanced course equips engineers with a complete end-to-end toolkit for finding, localizing, reproducing, and fixing failures across all layers of an Altera SoC design.

This hands on course builds deep practical mastery of the complete Altera in system debug suite available in Quartus Prime.

This course is offered as core material followed by two independent optional sessions. The core material provides the essential, device family agnostic foundation every engineer needs before working with any Altera FPGA or SoC FPGA.

This course provides embedded engineers and architects with an end-to-end understanding of Altera software development for the Hard Processor System (HPS)

This course introduces FPGA and SoC design concepts to engineers whose primary background is software development.

This advanced course elevates engineers from solid Platform Designer users to expert-level practitioners.

This course provides a comprehensive, structured approach to debugging software running on Altera SoC devices.

Partial Reconfiguration (PR) allows a defined region of an FPGA to be reconfigured at runtime while the remainder of the device continues to operate without interruption.

This advanced course focuses on performance critical optimization techniques for High Level Synthesis (HLS) on Altera FPGAs using the Altera HLS Compiler Pro Edition.

This course equips experienced engineers and architects with the knowledge and hands-on skills needed to integrate AI agents into modern System-on-Chip (SoC) design workflows.

This course prepares system architects, hardware engineers, and software engineers to apply AI agents and large language model (LLM) technology directly within their System-on-Chip (SoC) verification flows.

Building on Linux BSP fundamentals, this course dives deep into Linux kernel driver development for HPS peripherals and custom FPGA IP on Altera SoC devices.

This course provides engineers and architects with the knowledge and hands-on experience needed to develop high performance FPGA acceleration solutions using Intel’s oneAPI toolkit.

This course is the definitive program for engineers who want to master the complete Embedded Linux software stack on Altera SoC FPGA platforms.

This course covers the complete software stack for Altera SoC FPGA platforms.

This course is built for Altera SoC FPGA designers who want to develop deterministic, production grade real time systems using Zephyr RTOS on Altera SoC FPGA platforms.

This advanced course brings together all disciplines of Altera SoC FPGA design into a comprehensive system design and verification experience.

This course teaches engineers how to design, implement, verify, and optimize high performance DSP systems on Altera FPGA devices using both hand coded RTL HDL and Altera's production grade IP cores.

This foundational course provides hardware engineers, FPGA designers, and embedded software engineers with the machine learning and deep learning knowledge required to participate effectively in AI hardware acceleration projects.

This advanced course develops the skills to design, optimize, and integrate custom AI inference accelerator kernels using Altera HLS Compiler Pro, the Altera FPGA SDK for OpenCL, and RTL/SystemVerilog on Altera FPGAs.

This course provides FPGA engineers with a comprehensive, hands-on mastery of Synopsys Design Constraints (SDC) authoring and static timing analysis (STA) using the Quartus® Prime Pro Edition Timing Analyzer.

This course provides a comprehensive introduction to VHDL

This course provides a practical, hands-on foundation in using Verilog HDL for digital design.

This advanced, hands-on course is designed for experienced FPGA engineers who want to deepen their mastery of VHDL.

This course teaches designers to write professional, synthesizable RTL code using industry-standard Verilog HDL practices.

This course is aimed at RTL designers who wish to learn about the features of SystemVerilog for RTL design.

This course introduces engineers to developing comprehensive verification environments using SystemVerilog.

This course provides a comprehensive, ground-up treatment of the Altera Agilex FPGA and SoC device families.

This course provides engineers with a practical introduction to the Altera® FPGA primary development environment, Quartus Prime.

This course provides a comprehensive understanding of how to create and optimize FPGA design logic to take full advantage of the Hyperflex® architecture.

This course introduces the boot and configuration options and features available in Altera® FPGAs and SoCs.

This comprehensive course consolidates the full breadth of advanced FPGA design knowledge into a single intensive program.

This advanced course equips experienced FPGA engineers with the skills and methodology to achieve reliable, repeatable timing closure on complex Altera® FPGA designs using Quartus® Prime.

This course provides a thorough introduction to Altera's Platform Designer tool and guides engineers from beginner to intermediate proficiency.

This course provides comprehensive training in the Altera HLS Compiler Pro Edition.

This course teaches the uses and advantages of the Simics® Simulator for Altera® SoC FPGAs

This course provides a comprehensive introduction to the Altera Nios V soft-core processor and its ecosystem.

This course provides a foundation in Digital Signal Processing (DSP) theory while simultaneously building a professional Python-based prototyping and analysis workflow.

This course develops systematic and detailed understanding of the Altera FPGA device family and the Quartus Prime Pro ecosystem as applied to AI inference acceleration.

This course provides comprehensive, hands-on expertise with the Altera FPGA AI Suite.

This course builds deep practical mastery of the complete Altera in-system debug suite available in Quartus Prime.

This entry-level course establishes the foundational mindset, methodology, and vocabulary that every engineer needs before approaching a debug tool.

FPGA Authority is an Altera® authorized training partner delivering hands-on education led by certified experts with real-world design experience. Our focused training programs help engineers and design teams build practical skills across Altera devices, tools and flows.