Pro Edition
Design Flow
Platform Designer
Block Based Design
Partial Reconfiguration
Design Entry/Planning
Design Partition Planner
Chip Planner
Interface Planner
Logic Lock Regions
Multiprocessor Support (Faster Compile Time)
IP Base Suite
Placement and Routing
Fitter (Place and Route)
Register Retiming
Timing and Power Verification
Timing Analyzer
Design Space Explorer II
Power Analysis
Simulation and Debug
Signal Tap Logic Analyzer
Transceiver Toolkit
Questa* – Altera FPGA Edition