Intel® FPGA for PCI Express* IP

Figure 1. PCI Express Block Diagram

PCI Express* IP Performance Demonstration on Intel® Arria® 10 Device

1st Level Signal Tap IP Debug Feature

Push-Button Hardware Design Examples in Intel Quartus® Prime Software

PCI Express* (PCIe*) protocol is a high-performance, scalable, and feature-rich serial protocol with data transfer rates from 2.5 gigatransfers per second (GT/s) to 8.0 GT/s and beyond. Intel® FPGA PCI Express intellectual property (IP) continues to scale as the PCI-SIG* organization delivers next-generation specifications. Intel has been a member of PCI-SIG since 1992, and with each new generation of silicon, Intel continues to participate in PCI-SIG Compliance Workshops to ensure interoperability and conformance with current industry standards.

The PCI Express IP solutions include Intel’s technology-leading PCI Express hardened protocol stack, which includes the transaction and data link layers, and hardened physical layer, which includes both the physical medium attachment (PMA) and physical coding sublayer (PCS).  Intel's PCI Express IP also includes optional soft logic blocks, such as direct memory access (DMA) engines and single root I/O virtualization (SR-IOV). This unique combination of hardened and soft IP provides superior performance and flexibility for optimal integration.

Intel offers Intel FPGA IP function-based PCI Express IP solutions that are compliant with the Platform Designer (formerly Qsys). For more information, please contact your local Intel FPGA sales representative.

  • New hardened protocol stack on Intel Stratix® 10 device
    • Intel Stratix 10 device: 14 nm Intel Tri-Gate (FinFET) process    
  • 4th generation hardened protocol stack, PCS, and PMA layers
    • Four device generations
      • (65 nm, 40 nm, 28 nm, 20 nm)
    • Seven product families
  • Direct memory access (DMA) engine and device drivers built for best performance and efficiency
    • Highest throughput and input/output operations per second (IOPS) performance
      • Up to 6.8 gigabytes per second (GBps) of throughput and greater than 500K IOPS
    • Scatter-gather-based DMA
    • Linux* and Windows device drivers
      • Character and block device driver support
      • Open source code
      • License model is dual BSD/GPL
  • Gen1, Gen2, Gen3 support
  • x1, x2, x4, x8 lane widths (x16 lane width on the Intel Stratix 10 device)
  • Root port and endpoint configurations
  • SR-IOV feature
    • Four physical functions (PFs) / 2048 virtual functions (VFs)
    • MSI / MSI-X interrupt support
  • Configuration via protocol (PCIe) initialization (CvP Init) and update (CvP Update)
    • For power-up programming
  • Partial reconfiguration over protocol (PCIe) (PRoP)
    • For multiple image programming while powered
  • Multiple user interface options
    • Avalon® Streaming (Avalon-ST)
    • Avalon Memory-Mapped (Avalon-MM)
    • Avalon-MM with DMA

Table 1. Device Support and Number of Hardened PCI Express IP Blocks

Device Family Number of Hardened PCI Express IP Blocks PCI Express Link Speed

Gen1

(2.5 GT/s)

Gen2

(5.0 GT/s)

Gen3

(8.0 GT/s)

Intel Stratix 10 1 to 4 per device check mark check mark check mark
Intel Arria 10 1 to 4 per device check mark check mark check mark
Intel Cyclone® 10 1 per device check mark check mark  
Stratix V 1 to 4 per device check mark check mark check mark
Arria V 1 or 2 per device check mark check mark  
Intel Cyclone 10 GX 1 per device  check mark check mark  
Cyclone V GT 2 per device check mark check mark  
Cyclone V GX 1 or 2 per device check mark    
Stratix IV 2 to 4 per device check mark check mark  
Cyclone IV GX 1 per device check mark    
Arria II GZ 1 per device check mark check mark  
Arria II GX 1 per device check mark    

Table 2. Device Configurations and Features Support

Interface Type Avalon-ST Avalon-MM Avalon-MM with DMA SR-IOV CvP / PRoP
Device/Configuration  
Intel Stratix 10 Endpoint Up to Gen3 x16 Up to Gen3 x16 Up to Gen3 x16 Up to Gen3x16 Up to Gen3 x16: CvP Init and CvP Update
Root Port Up to Gen3 x16 Up to Gen3 x16 N/A N/A N/A
Intel Arria 10 Endpoint Up to Gen3 x8 Up to Gen3 x4 Gen1 x8, Gen2 x4, Gen2 x8, Gen3 x2, Gen3 x4, Gen3 x8 Available Up to Gen3 x8: CvP and PRoP
Root Port Up to Gen3 x8 Up to Gen3 x4 N/A N/A N/A
Intel Cyclone 10 GX Endpoint Up to Gen2 x4 Up to Gen2 x4 Gen2 x4 N/A Up to Gen2 x4: CvP and PRoP
Rootport Up to Gen2 x4 Up to Gen2 x4 N/A N/A N/A
Stratix V Endpoint Up to Gen3 x8 Up to Gen3 x4 Gen1 x8, Gen2 x4, Gen2 x8
Gen3 x2, Gen3 x4, Gen3 x8
Available Gen1: CvP Init and CvP Update
Gen2: CvP Init and CvP Update
Root Port Up to Gen3 x8 Up to Gen3 x4 N/A N/A N/A
Arria V GZ Endpoint Up to Gen3 x8 Up to Gen3 x4 Gen1 x8, Gen2 x4, Gen2 x8
Gen3 x2, Gen3 x4, Gen3 x8
N/A Gen1: CvP Init and CvP Update
Gen2: CvP Init and CvP Update
Root Port Up to Gen3 x8 Up to Gen3 x4 N/A N/A N/A
Arria V Endpoint Up to Gen1 x8 and Gen2 x4

Up to Gen1 x8 and

Gen2 x4 (no x2)

Gen1 x8, Gen2 x4 N/A Up to Gen1 x8 and Gen2 x4
Gen1: CvP Init and CvP Update
Gen2: CvP Init
Root Port Up to Gen1 x8 and Gen2 x4

Up to Gen1 x8 and

Gen2 x4 (no x2)

N/A N/A N/A
Cyclone V Endpoint Up to Gen2 x4 Up to Gen2 x4 (no x2) Gen2 x4 N/A Up to Gen2 x4
Gen1: CvP Init and CvP Update
Gen2: CvP Init
Root Port Up to Gen2 x4 Up to Gen2 x4 (no x2) N/A N/A N/A
Notes:
  1. Contact your local sales representative for details

Table 3. PCI Express IP Quality Metrics

Basics

Year IP was first released

2005

Latest version of Intel Quartus® Prime software supported

17.1

Status

Production

Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim*- Intel FPGA Edition
  • Timing and/or layout constraints
  • Documentation with revision control
  • Readme file
Y for all, except for providing Readme files

Any additional customer deliverables provided with IP

Testbench and design examples

Parameterization GUI allowing end user to configure IP

Y

IP core is enabled for Intel FPGA IP Evaluation Mode Support 

Y

Source language

Verilog and VHDL

Testbench language

Verilog

Software drivers provided

Y

Driver OS Support

Linux/Windows

Implementation

User interface

Avalon Streaming, Avalon Memory-Mapped

IP-XACT metadata

N

Verification

Simulators supported

NCSim, ModelSim, VCS/VCSMX

Hardware validated

Arria 10, Stratix 10

Industry standard compliance testing performed

Y

If Yes, which test(s)?

PCI-SIG*

If Yes, on which Intel FPGA device(s)?

Arria 10 GX

If Yes, date performed

April 2015

If No, is it planned?

N/A

Interoperability

IP has undergone interoperability testing

Y

If yes, on which Intel FPGA device(s)

Arria 10 GX

Interoperability reports available

Y

Intel offers a host of PCIe reference designs and application notes. These reference designs and application notes offer ready-made solutions that can be leveraged for feasibility studies, device selections, and design proofing on Intel FPGAs and SoCs.

The Intel FPGA development kits complement the reference designs and application notes by delivering a complete system-level design environment that includes both the hardware and software needed to immediately begin developing designs. Each reference design indicates which Intel FPGA development kit and version of the Quartus II or Quartus Prime (version 15.1 and above) software were used for its development cycle.

As PCIe is a very configurable IP solution and supports numerous application needs, we cannot offer reference designs for every configuration or application possible. If there is no readily available reference design for your particular configuration or device, you may use a similar design and modify and/or port it as needed to fit your design requirements.

Table 4 describes the various reference designs and application notes available for PCIe applications.

Table 4. Reference Designs and Application Notes

Name Application Note/
Wiki/
Other
Development Kit Used Intel Quartus Software Version Design Flow Platform Designer (formerly Qsys)/
Other
EP/RP1 AVST2/
AVMM3/
AVMM with DMA
User Interface Width/
PCIe Gen and Link Width/
Device Driver OS Support
PCIe WITH EXTERNAL MEMORY INTERFACE REFERENCE DESIGN

PCIe AVMM with DMA performance design example
(Linux)

Contact your sales representative for design  Arria 10 GX FPGA Development Kit 17.0 Platform Designer EP AVMM with DMA

256 bit / Gen3 x8

Linux

Stratix V GX FPGA Development Kit 15.1.2

256 bit / Gen3 x8

Linux

Cyclone V GT FPGA Development Kit

128 bit / Gen2 x4

Linux

PCIe AVMM with DMA performance design example
(Windows)

Contact your sales representative for design  Stratix V GX FPGA Development Kit 15.1.2
Platform Designer EP AVMM with DMA

256 bit / Gen3 x8 

Windows

Cyclone V GT FPGA Development Kit

128 bit / Gen2 x4

Windows

PCIe AVMM with DMA and DDR3 Memory Interface Design Store
Arria 10 GX FPGA Development Kit 17.0 Platform Designer EP AVMM with DMA

256 bit / Gen3 x8

Linux4

Altera Wiki Stratix V GX FPGA Development Kit 16.0.2
Altera Wiki

Arria V GX

Starter Kit

128 bit / Gen2 x4

Linux4

Altera Wiki Cyclone V GT FPGA Development Kit

128 bit / Gen2 x4

Linux4

PCIe WITH ON-CHIP MEMORY INTERFACE REFERENCE DESIGNS
PCIe AVMM with DMA and On-Chip Memory Interface Design Store
Arria 10 GX FPGA Development Kit 17.0 Platform Designer EP AVMM with DMA

256 bit / Gen3 x8

Linux4

Altera Wiki Stratix V GX FPGA Development Kit 16.0.2
Altera Wiki Arria V GT FPGA Development Kit

128 bit / Gen2 x4

Linux4

Altera Wiki

Arria V GX

Starter Kit

Altera Wiki Cyclone V GT FPGA Development Kit
PCIe WITH SINGLE-ROOT I/O VIRTUALIZATION (SR-IOV) REFERENCE DESIGN
PCIe AVMM with DMA and SR-IOV Interface Altera Wiki Stratix V GX FPGA Development Kit 14.0 Platform Designer EP AVMM with DMA

256 bit / Gen3 x8

PCIe WITH EXTERNAL MEMORY INTERFACE REFERENCE DESIGNS (Legacy Reference Designs)
PCIe AVST and On-Chip Memory Interface AN456 Arria 10 GX FPGA Development Kit 15.0 Platform Designer EP AVST

64 bit / Gen1 x1

128 bit / Gen2 x8

256 bit / Gen3 x4

Windows4

PCIe AVST and On-Chip Memory Interface Stratix V GX FPGA Development Kit

64 bit / Gen1 x1, Gen1 x4,

Gen2 x1, Gen3 x1
128 bit / Gen1 x8, Gen2 x4,

Gen2 x8, Gen3 x4

Windows4

PCIe AVST and On-Chip Memory Interface Arria V GT FPGA Development Kit

64 bit / Gen1 x1, Gen1 x4,

Gen2 x1
128 bit / Gen1 x8, Gen2 x4 
Windows4

PCIe AVST and On-Chip Memory Interface Cyclone V GT FPGA Development Kit

64 bit / Gen1 x1, Gen1 x4,

Gen2 x1
128 bit / Gen2 x4
Windows4

PCIe AVST and On-Chip Memory Interface Stratix IV GX FPGA Development Kit

64 bit / Gen1 x1, Gen1 x4,

Gen2 x1, Gen2 x4
128 bit / Gen1 x8, Gen2 x4,

Gen2 x8
Windows4

PCIe AVST and On-Chip Memory Interface Cyclone IV GX FPGA Development Kit Hardened Protocol Stack IP Use
64 bit / Gen1 x1, Gen1 x4
Soft Protocol Stack IP Use
64 bit / Gen1 x1
Windows4
PCIe AVST and On-Chip Memory Interface Arria II GX FPGA Development Kit

Hardened Protocol Stack IP Use
64 bit / Gen1 x1, Gen1 x4,

Gen1 x8
Soft Protocol Stack IP Use
64 bit / Gen1 x1, Gen1 x4
Windows4

PCIe AVST / AVMM and DDR2 / DDR3 Memory Interface AN431 Stratix IV GX FPGA Development Kit 11.0SP1 Platform Designer EP AVMM / AVST 64 bit / Gen2 x4
Windows (Jungo Driver)
Arria II GX FPGA Development Kit Hardened Protocol Stack IP Use
64 bit / Gen1 x4
Windows (Jungo Driver)
OTHER PCIe COLLATERAL ITEMS AND TOOLS
MSI-X Implementation Guidelines for Altera FPGAs Altera Wiki All 14.0 N/A EP AVMM / AVST N/A
Transceiver Toolkit for hardened PCIe IP (Gen1 x8) Altera Wiki Stratix V GX FPGA Development Kit
 
13.1 Platform Designer EP AVST 128 bit / Gen1 x8, Gen2 x8
256 bit / Gen3 x8
Transceiver Toolkit for hardened PCIe IP (Gen2 x8)
Transceiver Toolkit for hardened PCIe IP (Gen3 x8)
Notes:
  1. EP = Endpoint, RP = Root Port. 
  2. AVST = Avalon Streaming (Avalon-ST).
  3. AVMM = Avalon Memory-Mapped (Avalon-MM).
  4. Light features driver.

Documents

The following user guides are catalogued by user interface and feature function:

Please contact your local Intel FPGA sales representative for the following documents:

  • Intel Stratix 10 device vs. Intel Arria 10 / Stratix V device (PDF)
  • Avalon-ST PCIe IP Feature and Interface Differences Application Note (PDF)
  • Avalon-MM and Avalon-MM DMA PCIe IP Feature and Interface Differences Application Note (PDF)

For technical support on this Intel FPGA IP function, please visit the mySupport online issue tracking system. You may also search for related topics on this function in the Knowledge Database.

† Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase.  For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.