What's New in Embedded

17.0 Nios® II Processor and EDS New Features

Nios II Processor New Features

The Nios® II processor is now fully supported in Intel® Quartus® Prime Professional Edition and Intel Qsys Pro system integration tool.


Nios II Embedded Design Suite (EDS) New Features

Nios II Software Build Tools (SBT): Windows 10 host support added in Quartus Prime Pro Edition software.

Nichestack: updated drivers to support mSGDMA and the latest Triple-Speed Ethernet intellectual property (IP). Refer to the Using the NicheStack TCP/IP Stack - Nios II Edition Tutorial.


Embedded IP New Features

  • New Serial Flash Controller II and Generic Quad SPI controller II IPs with improved data performance
  • New Avalon® Streaming (Avalon-ST) Freeze Bridge IP to support partial reconfiguration
  • All embedded IPs now support compilation targeting Intel Cyclone® 10 devices
  • I2C Slave to Avalon Memory Mapped (Avalon-MM) Master:
      MM master write data corruption due to overrun of internal I2C slave RX shift logic issue fixed
  • Altera® Avalon FIFO IP:
      incorrect back pressure behaviour during reset state, and data loss when FIFO is almost full, issues fixed
  • EPCQ Controller:
      incorrect back pressure behaviour during reset state, issue fixed
  • Generic QSPI Controller IP:
      modified to enable support for multiple instances in one Qsys design and to support N25Q016 flash device
  • Serial Flash Controller IP:
      EPCS4 flash device now supported
  • The following IPs (present in Quartus Prime Standard version) are not present in Quartus Prime Professional version:
    •  Altera Avalon New SDRAM Controller
    •  Altera SDRAM Tristate Controller
    •  Altera Avalon EPCS Flash Controller
    •  Altera Avalon Compact Flash Controller
    •  Altera Avalon Half Rate Bridge
    •  Altera Avalon Pixel Converter
    •  Altera Avalon Video Sync Generator
    •  Altera Avalon LCD 16207
    •  Altera Avalon SGDMA
    •  Altera Modular ADC
    •  Altera SM Bus Controller

16.1 Nios II Processor and EDS New Features

Nios II Processor New Features

  • The Nios II processor is supported as a pre-release (beta) version in Quartus Prime Pro Edition software due to the changes required to support IP components in Qsys Pro
    Note: the Nios II (Classic) processor is not supported in Quartus Prime Professsional/Qsys Pro; it will continue to be supported in Quartus Prime Standard Edition software releases.

Nios II EDS New Features

  • The GCC (Nios II) toolchain has been upgraded to version 5.3
    (other upgrades include: binutils v2.25, gdb v7.10, newlib v2.2)
  • BSP editor - in previous releases there was an issue with storing the file generation settings (disable), the settings are now saved correctly and files with generation set to 'disable' remain disabled in subsequent sessions.
  • nios2-elf-gcc defaults to the option -mgpopt=local, but in ACDS 16.1 the software build tools always set -mgpopt=global in the makefile as, in general, this will deliver better compiler output. Compiling different source files with different -Gn settings and linking them together is not recommended.


Embedded IP New Features

  • New: I2C IP component.
  • The 16550 UART IP has been enhanced to support a user defined TX FIFO level trigger.

16.0 Nios II Processor and EDS New Features

Nios II Processor New Features

  • The floating-point hardware 2 (FPH2) has been enhanced to support the ability to include or exclude groups of custom instructions (arithmetic, square root, conversions, comparisons) so that developers can omit groups of instructions that are not needed and save logic resources. Support is automatically extended into the software when the board support package (BSP) is re-built.


Nios II EDS New Features

  • GCC (Nios II) has been upgraded to version 5.2


Embedded IP New Features

  • New: I2C slave to Avalon® Master Bridge IP
  • Feature enhancements to Intel® MAX® 10 FPGA analog-to-digital converter (ADC) interface IP
    • Support for variable ADC sampling frequencies (1 MHz->25 KHz)
    • ADC simulator is now able to read voltages from a text file and output a correct converted value
  • Maximum buffer size option for the 16550 UART IP has been increased

15.1 Nios II Processor and EDS New Features

Nios II Processor New Features

  • The FPH2 has been enhanced to support exclusion of the sqrt() custom instruction. The sqrt() instruction is a look-up table based implementation and relies on a pre-populated FPGA memory, however for some MAX 10 device configurations, FPGA memory block initialisation is not supported; this means that this instruction will not function correctly for those configurations. In these cases the instruction can be manually omitted from the FPH2 module and the sqrt() operation will be performed correctly in software.
  • For simplicity, the default name of the Gen2 cores in Qsys has been modified to omit the gen2 label, the register transfer level (RTL) name remains the same.
  • The Qsys graphical user interface (GUI) for the Nios II vectored interrupt controller (VIC) has been modified; a widget has been added that allows selection of the number of pipeline stages used in the core. The default value is five cycles latency but with the new GUI option this can be reduced, although the penalty for this is a reduction in the fMAX of the VIC.


Nios II EDS New Features

  • GCC has been upgraded to v4.9.2


GCC for Nios II v4.9.2 Release Notes

Code density and performance
Use of the -mgpopt=global setting is recommended as it generally deliver results with better code density *and* performance. (Note: this requires that everything is compiled with the same -Gn switch setting; use of -Gn is not generally recommended).

C++ code size reduction: -fno-exceptions
When a developer is using C++ but trying not to link in the (big) C++ exception-handling machinery nios2-elf-g++ will, in some cases, link in the exception-handling machinery where it is not actually required.  This switch suppresses that behaviour, which results in a smaller code footprint for those situations.

Response to address 0x00 access: -fdelete-null-pointer-checks
Developers often have RAM at address 0x00 (== NULL pointer in gcc and most C compilers). From gcc 4.9 onwards, by default gcc detects attempts to read or write to address 0x00 and converts them to traps; typically in embedded/Nios II-based  systems, these traps are not handled so the code will fail silently. This means that code that works when compiled with earlier versions of gcc could silently fail when compiled with gcc-4.9 (onwards).

In order to avoid this for Nios II this behaviour has been modified so that accesses to address 0x00 will work as expected for Nios II systems but there may be a slight negative effect on code performance. In Nios II systems that are known not to read/write RAM at address 0x00, use of the switch --fdelete-null-pointer-checks restores the original gcc behaviour and may provide a small performance boost.

Expansion of __builtin_trap
GCC now produces trap 3 instead of break 3 in the expansion of the __builtin_trap function and in other situations where a trap is emitted to indicate undefined runtime behaviour. This is for compliance with the Nios II ABI for Linux targets, which does not permit the use of the break instruction in user code.

Memory corruption bug fix
A bug in support for long pathnames on Windows hosts has been fixed that could lead to memory corruption, causing potential crashes and unpredictable behaviour.

GDB breakpoint instruction
GDB now uniformly uses trap 31 instead of a break instruction for software breakpoints. This is for consistency with the Nios II ABI for Linux* targets.

For more information on gcc, see:


Embedded IP New Features

  • The 16550 UART IP has been updated to add support for 9 bit data and sticky bit.
  • A descriptor prefetcher capability has been added to the mSGDMA IP to support the ability to automatically fetch descriptors from memory. 

15.0 Nios II Processor and EDS New Features

Nios II processor New Features

  • VHDL simulation capability for Nios II has been fixed


Nios II EDS New Features:

  • MAX 10 ADC HAL driver
  • Quad serial peripheral interface (SPI) HAL driver
  • Enhancements to the MAX 10 ADC interface IP and HAL driver
  • Nios II GNU Toolchain upgraded to 4.9.1
    • Improved support for link time optimization (-flto)
    • More control over global pointer optimization using
    • New NULL pointer check functionality of 4.9.1 can be disabled with –fno-delete-null-pointer-checks
  • High-profile defects resolved:
    • EPCQ HAL driver repaired
    • Custom Newlib Generator on Windows fixed
    • Nios II terminal standard input on Windows now working
  • Nios II Linux kernel and all tool-chain components have been accepted upstream


Embedded IP New Features

  • Enhancements to the MAX 10 FPGA ADC interface IP and HAL driver
  • Nios II flash accelerator IP option (Beta) for operating from UFM with increased performance
  • MAX 10 FPGA dual ADC simultaneous sampling capability
  • Generic quad SPI controller IP production release and HAL driver
  • Remote update IP for MAX 10 FPGA with HAL drivers
  • Minor bug fixes to mSGDMA IP and EPCQ controller IP

14.1 Nios II Processor and EDS New Features

Nios II processor New Features

  • Nios II Gen2 is released with production status (no longer preview)
  • Nios II Gen1 is now called “Nios II (Classic)”


Nios II EDS New Features:

  • Eclipse GUI upgrade to version 4.3
  • Nios II software toolchain improvements :
    • Link time optimization enabled [-flto]
    • Upgrades: GCC v4.8.3, Newlib v1.18, GDB v7.7
    • Windows build time performance improvements à 3X faster to build webserver
  • 64 bit support for host tools that were still 32 bit in 14.0
    • 64 bit nios2-gdb-server
    • 64 bit nios2-flash-programmer
    • 64 bit nios2-terminal
  • Nios II Gen2 support for MAX 10 FPGA
    • UFM MemInit for synthesis and simulation
    • UFM Bootloader software support
  • EPCQ software support in BootLoader and Nios II HAL
  • The Nios II version of Linux has been posted upstream


Embedded IP New Features

  • The EPCQ controller IP has been upgraded to support x4 mode and EPCQ-L device support
  • A beta version of the generic quad SPI controller IP was released
  • The MAX 10 FPGA flash controller IP that interfaces the MAX 10 FPGA flash memory to the FPGA logic was released

14.0 Nios II Processor and EDS New Features

Nios II Gen2 Processor Support

ACDS v14.0 introduces software (binary) compatible new (preview) implementations of the Nios II processor cores. The Nios II EDS contains minor changes to support the additional features of the new Nios II Gen2 processor cores so it is recommended that users re-generate the BSP and rebuild the application when using the Gen2 cores. The Nios II Gen2 processor core changes compared to the previous Nios II core versions include:

  • Improved Qsys GUI wizard
  • Removal of Nios II /s core option (note: the same configuration as the /s can now be achieved by configuring the Nios II Gen2 /f core appropriately)
  • Nios II Gen2 /f core updates:
    • Optional 32 bit address range
    • Optional peripheral (uncached) memory region (configurable size, for use when 32 bit address range is selected)
    • When an uncached write is made, the cache is no longer updated, hence software developers should take this into account in their code
    • Optional static branch prediction
    • Optional error correction code (ECC) on data cache and tightly-coupled memories (instruction and data)
    • Higher performance multiply (32 bit mult. 5 cycles -> 1 cycle)
    • On average, higher-performance divide that is more deterministic
    • 64 bit multiply supported on all devices (not just those with digital signal processing (DSP) blocks)
    • Improved low-cost shifter implementation (1 bit/cycle -> 4 bits/cycle)
    • Instruction cache is now optional even when JTAG debug present
    • More flexible configuration of JTAG Debug options (i.e. numbers of hardware breakpoints, triggers)
    • Off-chip trace now has an Avalon streaming (Avalon-ST) interface (requires addition of IP to bridge Avalon-ST -> trace probe connection, available from trace tool vendors)

MAX 10 and Intel Arria® 10 FPGAs are only supported by Nios II Gen2 processors. The previous generation of Nios II processors are not supported with MAX 10 or Arria 10 FPGAs.


Nios II EDS 14.0 Updates and Fixes

The v14.0 Nios II Software Build Tools (SBT) only runs on 64 bit hosts systems, 32 bit hosts are no longer supported (gdb-server and the flash programmer remain 32 bit).
Run time stack checking has now been fixed and the compiler now supports long jumps (>256Mb) correctly. The address span expander and IRQ bridge IP are now fully supported.

13.1 Nios II Processor and EDS New Features

  • GCC upgrade to v4.7.3
    The v13.1 Nios II EDS/SBT supports v4.7.3 version of GCC for smaller code size and compatibility with the latest versions of currently available from rocketboards.org.
  • Enhanced floating-point custom instruction support
    Get the option to select a new floating-point custom instruction set component in the Qsys tool. The component has one combinatorial custom instruction and one multi-cycle custom instruction. The combinatorial custom instruction implements comparison, minimum, maximum, negate, and absolute operations. The multicycle custom instruction implements add, subtract, multiply, divide, square root, and conversion operations. These are binary compatible with the previous custom instructions, but offer superior performance (fewer cycles operation).
  • ECC support
    The optional ECC in the Nios II configuration wizard enables ECC protection on the RAMs inside the processor core and the instruction cache (data cache with ECC enabled is currently not supported). Single-bit soft errors are corrected and dual-bit soft errors cause either an instruction cache flush or processor exception. Only available on the Nios II /f core without data cache.
  • RTL Nios II processor trace simulation support
    This feature enables recording and time-stamping of Nios II processor instruction execution during RTL simulation in ModelSim*-Intel software edition of events such as instruction execution and address, data address and value, interrupts, and control register changes.The timestamp allows the developer to align hardware simulation data with software execution.