Reduce Time to TÜV Certification

To simplify and speed up your safety certification process, Intel worked closely with TÜV Rheinland to provide a IEC61508 certified Functional Safety Data Package, which includes:

  • Intel® FPGAs
  • Diagnostic and standard intellectual property (IP) such as the Nios® II processor
  • FPGA design flows including a safety separation design flow
  • Development tools, including the Intel Quartus® Prime design software

TÜV-Qualified FPGAs for Functional Safety Designs

Our certified Safety Integrity Level 3 (SIL3) Functional Safety Data Package shortens IEC 61508 development time and reduces certification risks in safety-critical industrial applications, such as industrial servo and inverter drives, safety devices, and automation controllers. The Safety Separation Design Flow retains the FPGA benefit of quick upgrades/bug fixes while reducing the need for full design re-certification. Our customers have been using the package since 2010 for industrial and automotive applications certified for ISO 26262, medical equipment, and military and aerospace systems. The following figure shows a typical dual-channel SIL3 industrial "safe" system implemented with two FPGAs. Contact your local Intel® FPGA representative for more information and access to the IP-ABG-SafetyDP4 (1 year), the IPR-ABG-SafetyDP4 (renewal) packages or example designs.

Typical Dual-Channel SIL3 Industrial "Safe" System Implemented with Two FPGAs

  • Guidelines on how to use the approved Intel FPGA development methodology and tools to design IEC 61508 certifiable systems
  • FMEDA tool allows calculation of failure rates and safe failure fraction (SFF) for Cyclone V SoC designs
  • Functional Safety Silicon Integration application note, showing how to qualify devices using the reliability report
  • Functional Safety Tools and Tool Flow application note, showing how to use the Intel Quartus Prime design software and develop FPGA systems according to IEC 61508
  • Diagnostic IP with IEC 61508 standard documentation and source code to monitor the integrity of the FPGA, memory, and clock signals
  • Comprehensive guidelines on using the data to correctly calculate failure in time (FIT) rates of FPGA devices and systems required for safety certification
  • Latest FPGA device reliability reports
  • TÜV Rheinland qualification certificate

Qualification data at the FPGA device level means you can benefit from the flexibility of FPGAs without having to provide the required data and assessment for the IEC 61508 or equivalent standards. Normally, you would have to collect and document device and tool data for submission to the assessor. With Intel's® Functional Safety Data Package, the device qualification process has been done for you. According to some of our customers, you can reduce system development time by up to two years from start to certification. TÜV is one assessor, and their standards are honored by the network of functional safety assessors.

The RTL coding guidelines can be used to improve code quality and reliability while helping to comply with requirements in the IEC 61508 standard.

Assessing your design for safety certification can be seamless. By following and adopting our FPGA-based certified design flow and methodology, as well as utilizing the included checklists, you can ensure high-quality project management and provision of the right project documentation.

To learn more about functional safety, please download the Developing Functional Safety Systems with TÜV-Qualified FPGAs (PDF) white paper and Reducing Steps to Achieve Safety Certification (PDF) white paper.

The Safety Separation Design Flow retains the FPGA benefits of quick upgrades/bug fixes while reducing the need for full design re-certification. The design flow guarantees that when changes are applied to non-safety regions, the safety regions are fully preserved, providing evidence that the placement and routing in the safety regions are identical to a previously certified design. To learn more about the Safety Separation Design Flow, please download the application note FPGA-based Safety Separation Design Flow for Rapid IEC 61508 Certification and contact your local Intel FPGA representative for further information and access to the design example.

The Nios II Lockstep solution was developed by Intel to enable safety designers to utilize the flexibility of the already certified Nios II processor, bringing their solutions to market, while meeting the stringent requirements of safety certification.

The lockstep solution provides high diagnostic coverage, self-checking and advanced diagnostic features in full compliance with functional safety standards IEC 61508 and ISO 26262, while reducing the need for difficult to develop and performance sapping diagnostic software test libraries.

Applications for the Nios II lockstep solution include advanced motor control safety features such as SS1, SS2 in conjunction with safety encoder, and functional safety over industrial ethernet applications.

The Nios II processor IP includes synthesizable register transfer level (RTL), safety manual, user guide and out of the box testbench. Contact your local Intel® representative for further information and access to the IP.

The Nios II QKit was developed by Validas AG to enable software designers to qualify the use of Nios II Toolchain in their safety application, fulfilling the requirements of IEC 61508 up to SIL 4 and ISO 26262 up to ASIL D.

Developing systems with the Nios II environment integrates parts of the Newlib library into the system. Therefore the Nios II QKit also supports library qualification of newlib by executing the contained library test cases on the target hardware.

The Intel Newlib library qualification kit contains:

  • 2.4 million test cases in 4.600 files with 42.000 functions / equivalence classes
  • Covers over 70 main functions of the newlib library
  • Coverage reports showing the completeness of the tests for the Newlib library
  • Qualification support tool to run tests on the target hardware and generate documents
  • V&V Report and TÜV certificate
  • Qualification user guide
  • Document templates


Contact your local Intel representative for further information and access to the Nios II QKit

The SafeFlex functional safety reference board and associated reference designs are designed by Intel and NewTec to reduce customer design effort for safety designs requiring IEC 61508 certification up to SIL3 and IEC 13849 PLe Cat 4. The board includes a reference design of a safety application together with documents describing the steps required to complete safety design from development of safety concept through to end product.

Contact NewTec for more information and to purchase the SafeFlex board.