Intellectual Property (IP)
Title
User Guides
SmartVID Controller User Guide
Altera Fault Injection IP Core User Guide
Altera Error Message Register Unloader IP Core User Guide
Ethernet Design Example Components User Guide
ALTDLL and ALTDQ_DQS IP Core User Guide
ALTDLL_ALTDQ_DQS_DesignExample_ex1 (42 KB)
ALTDLL_ALTDQ_DQS_DesignExample_ex2 (796 KB)
ALTDLL_ALTDQ_DQS_ex1_msim (397 KB)
ALTDLL_ALTDQ_DQS_ex2_msim (416 KB)
CORDIC IP Core User Guide
Random Number Generator IP Core User Guide
Altera Remote Update IP Core User Guide
altremote_update_designexample_rsu.zip (10.5 MB)
 
Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) IP Cores User Guide
altddio_DesignExample_ex1.zip (112 KB)
altddio_DesignExample_ex2.zip (140 KB)
altddio_ex1_msim.zip (18 KB)
altddio_ex2_msim.zip (17 KB)
SDI II IP Core User Guide
Altera PHYLite for Parallel Interfaces IP Core User Guide
ALTDQ_DQS2_nand_flash_example_131.qar (92 KB)
nand_flash_example_14.0a10.qar (167 KB)
PHYLite_delay_calculations.xlsx (27 KB)
Altera Transceiver PHY IP Core User Guide
Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide
user_led.zip (4 KB)
CPRI v6.0 MegaCore Function User Guide
Partial Reconfiguration IP Core User Guide
Video and Image Processing Suite User Guide
ALTDQ_DQS2 IP Core User Guide
top_AV_13.0sp1.qar (65 KB)
Top_SV_13.0sp1.qar (69 KB)
Altera ASMI Parallel IP Core User Guide
(The Altera ASMI Parallel megafunction IP core provides access to erasable programmable configurable serial (EPCS) and quad-serial configuration (EPCQ) devices through parallel data input and output ports.)
Altera GPIO Megafunction User Guide
Altera High-Definition Multimedia Interface IP Core User Guide
Altera LVDS SERDES IP Core User Guide
Altera User Flash Memory (ALTUFM) IP Core User Guide
alt_ufm Archive Files (72 KB)
alt_ufm ModelSim Files (16 KB)
Arria 10 Avalon-ST Interface for PCIe Solutions User Guide
Arria 10 Avalon-ST Interface with SR-IOV for PCIe Solutions User Guide
Arria 10 Native Fixed Point DSP IP Core User Guide<
Arria V Avalon-MM Interface for PCIe Solutions User Guide
Arria V Avalon-ST Interface for PCIe Solutions User Guide
Avalon Verification IP Suite User Guide
(Includes Qsys tutorials for Verilog HDL and VHDL)
Avalon Verification IP Suite Design Files (46 KB)
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
Embedded Peripherals IP User Guide
Floating-Point Megafunctions User Guide
Floating-Point Megafunctions Design Examples (32 MB)
Integer Arithmetic IP Core User Guide
altaccumulate_DesignExample.zip (90 KB)
altecc_DesignExample1.zip (79 KB)
altecc_DesignExample2.zip (115 KB)
altmemmult_DesignExample.zip (186 KB)
altmult_accum_DesignExample.zip (105 KB)
altmult_add_DesignExample.zip (77 KB)
altmult_complex_DesignExample.zip (156 KB)
altsqrt_DesignExample.zip (198 KB)
parallel_adder_DesignExample.zip (97 KB)
Introduction to Altera IP Cores
IP Compiler for PCI Express User Guide
JESD204B IP Core User Guide
Altera JESD204B RX Address Map and Register Definitions (465 KB)
Altera JESD204B TX Address Map and Register Definitions (356 KB)
Low Latency Ethernet 10G MAC User Guide
Design Examples for Low Latency 10G Ethernet MAC User Guide
LVDS SERDES Transmitter / Receiver (ALTLVDS_TX and ALTLVDS_RX) IP Core User Guide
altlvds_DesignExample.zip (203 KB)
altlvds_DesignExample_ex2.zip (113 KB)
altlvds_DesignExample_ex3.zip (252 KB)
altlvds_DesignExample_ex4.zip (31 KB)
altlvds_DesignExample_ex5.zip (12 KB)
altlvds_ex1_msim.zip (92 KB)
altlvds_ex2_msim.zip (58 KB)
altlvds_ex3_msim.zip (104 KB)
altlvds_ex4_msim.zip (433 KB)
Phase-Locked Loop Reconfiguration IP Core User Guide (ALTPLL_RECONFIG)
altpll_reconfig_DesignExample_ex1.zip (167 KB)
altpll_reconfig_DesignExample_ex2.zip (189 KB)
altpll_reconfig_DesignExample_ex3.zip (316 KB)
altpll_reconfig_ex1_msim.zip (68 KB)
altpll_reconfig_ex2_msim.zip (68 KB)
altpll_reconfig_ex3_msim.zip (432 KB)
RAM Initializer Megafunction User Guide (ALTMEM_INIT)
DE1_internalROM.zip (8 KB)
DE2_externalROM.zip (10 KB)
RAM-Based Shift Register (ALTSHIFT_TAPS) IP Core User Guide
DE_altshift_taps.zip (5 KB)
SCFIFO and DCFIFO Megafunctions User Guide
DCFIFO Design Example (33 KB)
skew_report.tcl (3 KB)
Serial Digital Interface (SDI) MegaCore Function User Guide
SerialLite II IP Core User Guide
Stratix V Avalon-MM Interface for PCIe Solutions User Guide
Triple Speed Ethernet MegaCore Function User Guide
100G Interlaken MegaCore Function User Guide
10-Gbps Ethernet MAC MegaCore Function User Guide
40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide
50G Interlaken MegaCore Function User Guide
8B10B Encoder/Decoder MegaCore Function User Guide
Altera Advanced SEU Detection IP Core User Guide
Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide
Altera OCT Megafunction User Guide
Altera Phase-Locked Loop (Altera PLL) Megafunction User Guide
Altera Unique Chip ID (ALTCHIP_ID) IP Core User Guide
ALTPLL (Phase-Locked Loop) IP Core User Guide
ddr_clk.zip (98 KB)
ddr-clk-msim.zip (6 KB)
shift_clk.zip (387 KB)
shift_clk_msim.zip (10 KB)
Arria 10 Avalon-MM DMA Interface for PCIe Solutions User Guide
Arria 10 Avalon-MM Interface for PCIe Solutions User Guide
Arria V GZ Avalon-MM Interface for PCIe Solutions User Guide
Arria V GZ Avalon-ST Interface for PCIe Solutions User Guide
Arria V Hard IP for PCI Express User Guide, v13.1
ASI MegaCore Function User Guide
Avalon Verification IP Suite v11.0 User Guide
Clock Control Block IP Core User Guide (ALTCLKCTRL)
CPRI IP Core User Guide
CRC Compiler User Guide
Cyclone V Avalon-MM Interface for PCIe Solutions User Guide
Cyclone V Avalon-ST Interface for PCIe Solutions User Guide
DDR and DDR2 SDRAM Controller Compiler User Guide
DisplayPort MegaCore Function User Guide
Dynamic Calibrated On-Chip Termination Megafunction User Guide (ALTOCT)
alt_oct_SV.zip (36 KB)
External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide
FIR Compiler User Guide
First-In-First-Out Partitioner Megafunction User Guide (FIFO Partitioner)
HyperTransport MegaCore Function User Guide
I/O Buffer (ALTIOBUF) IP Core User Guide
altiobuf_design_example_1.zip (56 KB)
altiobuf_ex1_msim.zip (91 KB)
Interlaken MegaCore Function User Guide
Internal Memory (RAM and ROM) IP Core User Guide
Internal_Memory_DesignExample.zip (33 KB)
Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide
Mentor Verification IP Altera Edition AMBA AXI3/4TM User Guide
Mentor Verification IP Altera Edition AMBA AXI4-Lite User Guide
Mentor Verification IP Altera Edition AMBA AXI4-Stream User Guide
PCI Compiler User Guide
POS-PHY Level 2 and 3 Compiler User Guide
POS-PHY Level 4 IP Core User Guide
QDRII SRAM Controller MegaCore Function User Guide
RapidIO II MegaCore Function User Guide
RapidIO MegaCore Function User Guide
RLDRAM II Controller MegaCore Function User Guide
SDI Audio IP Cores User Guide
SerialLite III Streaming MegaCore Function User Guide
Shift Register IP Core User Guide (LPM_SHIFTREG)
lpm_shiftreg Design Files Archive Example 1 (84 KB)
lpm_shiftreg Design Files Example 1 (80 KB)
lpm_shiftreg Design Files Archive Example 2 (75 KB)
lpm_shiftreg Design Files Example 2 (70 KB)
lpm_shiftreg ModelSim Files Example 1 (5 KB)
lpm_shiftreg ModelSim Files Example 2 (4 KB)
Stratix GX Transceiver User Guide
Stratix II GX Embedded Gigabit Ethernet MAC/PHY User's Guide
Stratix V Avalon-ST Interface for PCIe Solutions User Guide
Stratix V Avalon-ST Interface with SR-IOV for PCIe Solutions User Guide
Temperature Sensor (ALTTEMP_SENSE) Megafunction User Guide
alttemp_sense_ex1.zip (11 KB)
Virtual JTAG IP Core User Guide
sld_virtual_jtag - Design Example 1 (140 KB)
sld_virtual_jtag - Design Example 2 (304 KB)
V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide
Application Notes
AN 733: Altera JESD204B IP Core and TI ADC12J4000 Hardware Checkout Report

AN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit 
AN 729 Reference Design Files

AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Arria 10 Devices
AN 719: Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report
AN 712: Altera JESD204B IP Core and ADI AD9625 Hardware Checkout Report
AN 710: Altera JESD204B IP Core and ADI AD9680 Hardware Checkout Report
AN 696: Using the JESD204B MegaCore Function in Arria V Devices
Altera JESD204B MegaCore Function and ADI AD9250 Hardware Checkout Report (1 MB)
AN 696 Reference Design Example (3 MB)
AN 690: PCI Express DMA Reference Design for Stratix V Devices
AN661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig Megafunctions
PLL_DynamicPhaseShift.qar (88 KB)
PLL_MIFstreaming.qar (67 KB)
PLL_Reconfig_DPS.qar (48 KB)
PLL_Reconfig_MNC.qar (48 KB)
PLL_Reconfig_Qsys.qar (746 KB)
PLL Reconfiguration Calculator (30 KB)
AN653: Implementing the CPRI Protocol using the Deterministic Latency Transceiver PHY IP Core
an653_Reference_Design_File (346 KB)
AN 513: RapidIO Interoperability With TI 6482 DSP Reference Design
AN 392: Implementing Multiple Legacy DDR/DDR2 SDRAM Controller Interfaces
three controller example (26 KB)
two controller example (15 KB)
AN 380: Test DDR or DDR2 SDRAM Interfaces on Hardware Using the Example Driver
AN 361: Interfacing DDR & DDR2 SDRAM With Cyclone II Devices
AN 359: POS-PHY Level 4 MegaCore Function Parameter Selection Calculator
Parameter Selection Calculator (2 MB)
AN 349: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices
AN 348: Interfacing DDR SDRAM with Cyclone Devices
AN 343: OpenCore Evaluation of AMPP Megafunctions
AN 320: OpenCore Plus Evaluation of Megafunctions
White Papers
Enabling Improved Image Format Conversion with FPGAs
High-Definition Video Deinterlacing Using FPGAs
Radar Processing: FPGAs or GPUs?
Errata Sheets
Altera IP Release Notes 
(All IP and Nios II release notes are combined into one document)