Design Examples

Design examples are HDL code samples to help you get started with Intel® FPGA products. All examples can be used as a starting point for your own designs, and some examples are customized for specific development kits.  Ready-to-use design examples deliver efficient solutions to design problems. Use these examples to instantiate individual building blocks for use in a system design. For example, variations of external memory controller applications targeting Stratix®, Arria®, and Cyclone® FPGA families. Additional design examples can be found as associated with application notes and user guides.

SoC design examples are ready-to-use hardware and software projects that can be used as a starting point to evaluate and use the features of Intel SoC FPGAs. 

Design entry or tool examples highlight the design entry process. They include samples of instantiating basic logic blocks, scripting, gate-level timing simulation tools, and debugging. Some examples of Quartus® Prime software functions are also available. For more information about the different design entry methods, refer to the Help files in the Quartus Prime software.

Designs targeted for the MAX® 10 FPGA family and its development kits are available in the new Design Store.

Design Examples
Device Targeted Development Kits Supported Qsys Compliant Quartus II Version
Cyclone III
Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition
- 10.0
Design Examples
Device Targeted Development Kits Supported Qsys Compliant Quartus II Version
- - - 9.1
- - - -
- - - 9.1
- - - 7.1
- - - -
- - - -
Cyclone III , Stratix II
Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition, Altera Embedded Systems Development Kit, Cyclone III Edition, Nios II Development Kit, Stratix II Edition
- 9.0
Cyclone III
Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition, Altera Embedded Systems Development Kit, Cyclone III Edition
- 8.1
- - - -
Stratix II , Cyclone II
- - 9.0
- - - -
- - - 7.2
- - - -
Design Examples
Device Targeted Development Kits Supported Qsys Compliant Quartus II Version
- - - 7.2
- - - -

Our SoC series offers a balance of hardware performance, low power, form factor, and cost. Because the SoCs integrate many hard intellectual property (IP) blocks, you can lower your overall system cost, power, and design time.

The design examples provided target the following development kits:

Each design example is accompanied by a design archive and readme file. Instructions about importing the design archive, compiling the design software, running the executable, and the expected terminal output are all provided in the readme file for each design.

Other design examples can be found on the SoC RTOS and HWLIBs Support page as well as on Rocketboards.

Table 1: SoC Design Examples

Design Name Description File/Webpage Readme
SDMMC GSRD The Golden System Reference Design (GSRD) provides essential hardware and software system components that can be used as a starting point for various custom user designs. User Manual Arria 10 -
QSPI GSRD

Example

Arria 10

-
SGMI GSRD Release Notes Arria 10 -
NAND GSRD Coming Soon Coming Soon
Remote Update This project provides an example on how the user can remotely update the hardware and software running on an Altera Arria 10 SoC through a web interface.

Example

Arria 10

-
Remote Debug This example explains how to perform remote system debugging with the System-Level Debugging (SLD) tools.

Example

Arria 10

-
HPS-to-FPGA Bridges This design example exercises the memory mapped interfaces of the hard processor system (HPS) exposed to the FPGA fabric. The design performs memory tests by writing and reading the HPS memory using various ports of the HPS and measures the performance of the data movements.

Example

Readme-A10

Readme-CV

PCIe Root Port This reference design demonstrates a PCIe root port running on an Arria 10 SoC Development Kit connected to either a Cyclone V GT FPGA Development Kit PCIe end point or a generally available Intel PCIe Ethernet adapter card end point. It is also applicable on Cyclone V SoC Development Kit and Arria V SoC Development Kit.

Example

Arria 10

Arria V

Cyclone V

-
Secure Boot This document provides methods and design examples for implementing an Arria 10 SoC secure boot system using tools from the SoC Embedded Design Suite (SoC EDS) to secure the second-stage boot loader image.

Example

Arria 10

-
HPS DMA This HWLIB design example demonstrates how the DMA APIs are used to initialize the DMA, perform memory to memory transfers, and zero to memory transfers. Example-AV
Example-CV
Readme-AV
Readme-CV
Error correction code This HWLIB design example demonstrates the error correction code (ECC) APIs features for on-chip RAM, SD/MMC, quad serial peripheral interface (SPI), DMA and L2 cache. The example shows how to setup and enable ECC for each RAM, inject single/double bit errors and setup the interrupts for single/double bit error detections. Example-AV
Example-CV
Readme-AV
Readme-CV
GPIO This HWLIB design example demonstrates the usage of general-purpose input/output (GPIO) APIs to setup GPIO as output ports to drive HPS LEDs, and to setup GPIO as input ports for HPS push buttons. Example-AV
Example-CV
Readme-AV
Readme-CV
I2C This HWLIB design example demonstrates the usage of I2C APIs to perform master read/write and slave read/write. This example demonstrates I2C communication with LCD screen, EEPROM memory as well as communication between two I2C modules. Example-AV
Example-CV
Readme-AV
Readme-CV
Quad SPI This HWLIB design example demonstrates the usage of quad SPI APIs to perform reading and writing to the quad SPI with generic block I/O functions, perform data transactions using indirect mode and DMA mode. The example also demonstrates additional API features such as setting up MMU and caches. Example-AV
Example-CV
Readme-AV
Readme-CV
SD/MMC This HWLIB design example demonstrates the usage of SD/MMC APIs to initialize SD/MMC card, read and write using block I/O functions. Example-AV
Example-CV
Readme-AV
Readme-CV
Timer This HWLIB design example demonstrates how to use the Timer APIs for free-running timer, one-shot timer, watchdog timer, and global timer measurements. Example-AV
Example-CV
Readme-AV
Readme-CV
Unhosted This HWLIB design example shows how to use UART for printf output instead of semihosting. It also demonstrates how to boot a bare-metal program from a SD card. Example-AV
Example-CV

Readme-AV
Readme-CV

SPI This HWLIB design example demonstrates the usage of the SPI APIs to communicate between two SPI modules connected through the FPGA fabric.

Example-AV

Example-CV

Readme-AV

Readme-CV

HPS Peripheral Mapping to FPGA This design example shows how to route the hard processor system (HPS) EMAC and I2C peripherals into the FPGA fabric and connect them to FPGA I/O. Example Readme
Power Optimization This HWLIB design example illustrates the use of WFI or WFE calls that put the calling processor core into clock gating mode to save power. Example Readme
Shared Memory Partition  This design examples illustrates how to configure and test the memory protection rules for the hard processor system (HPS) SDRAM Controller. Example Readme

 

Related Links

Other Examples

 

Intel design examples are intended for the use of registered users of Intel FPGA devices and tools who have a valid Quartus II or Quartus Prime software license. To purchase Quartus II Subscription Edition software, visit the eStore or contact your local distributor.

 

Design Examples Disclaimer

These design examples may only be used within Intel Corporation devices and remain the property of Intel. They are being provided on an "as-is" basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Intel expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Intel.