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IntelliProp SATA Bridge Platform with Hardware Datapath IP Core (IPP-SA143A-1BR)

The IntelliProp IPP-SA143A-1BR is a high-performance SATA Bridge Platform with an integrated Hardware Datapath (Sandbox). It allows for seamless host-to-target communication while providing a dedicated logic area for "bump-in-the-wire" data manipulation, protocol analysis, or custom RTL insertion at full 6Gb/s wire speeds.

IntelliProp SATA Bridge Platform with Hardware Datapath with AES IP Core (IPP-SA143A-2BR)

The IntelliProp IPP-SA143A-2BR is an advanced SATA Bridge Platform featuring a high-performance hardware datapath with integrated AES encryption. It provides a secure, "bump-in-the-wire" solution for real-time data-at-rest security and custom data processing between a SATA host and target at full 6Gb/s wire speeds.

IntelliProp SATA Host App IP Core (IPC-SA101A-HI)

The IntelliProp IPC-SA101A-HI is a high-performance SATA Host Controller IP core that provides a simplified application interface for seamless communication with SATA storage devices. It offloads complex SATA protocol management to hardware, enabling high-speed data transfers with minimal FPGA resource utilization and no firmware requirement.

IntelliProp SATA Port Multiplier with Sandbox (IPP-SA128A-PM)

The IntelliProp IPP-SA128A-PM is a high-performance SATA Port Multiplier IP core with an integrated hardware "Sandbox." It enables a single SATA host to communicate with up to 15 SATA devices while providing a dedicated logic area for real-time, inline data manipulation and protocol analysis.

IntelliProp SATA RAID IP Core (IPC-BL109A-RD)

The IntelliProp IPC-BL109A-RD is a hardware-only SATA RAID 0 IP core designed to maximize storage performance and capacity. It enables high-speed data striping and concatenation across multiple SATA endpoints with ultra-low latency and zero firmware overhead, making it ideal for high-throughput Altera FPGA storage applications.

Interlaken IP

Interlaken is an interconnect protocol for high-speed, channelized chip-to-chip interface in networking applications. It is optimized for high-bandwidth chip-to-chip packet transfers at rates from 10 Gbps to 600 Gbps and beyond.

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Intra-vasular Ultrasound (IVUS), High Speed Data Acquisition

Intra-vasular Ultrasound (IVUS), High Speed Data Acquisition

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Introduction to Nios V Processors

This course provides a comprehensive introduction to the Altera Nios V soft-core processor and its ecosystem.

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Introduction to Platform Designer

This course provides a thorough introduction to Altera's Platform Designer tool and guides engineers from beginner to intermediate proficiency.