Quartus® Prime Design Software

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A powerful, integrated design environment built to scale with your FPGA designs. From design entry and synthesis to optimization, verification, and simulation, Quartus Prime supports every step of development—enabling advanced performance on devices with millions of logic elements.

WHAT'S NEW

What's New in Version 26.1

In Quartus Prime Design Software Ver. 26.1

Visual Designer Studio

Next-generation system design environment integrated directly into Quartus Prime Pro
Intuitive block-based design entry with drag-and-drop system creation
Smart connectivity automation simplifies IP integration and system assembly
Dynamic connectivity view enables fast editing of complex interconnects
Integrated IP catalog and AXI-based interfaces accelerate embedded system development
Seamless RTL integration with support for Verilog, VHDL, and SystemVerilog
Improved performance and responsiveness for faster IP invocation and system generation
Built-in example designs help developers quickly prototype embedded and AI systems

Installation & Licensing

Driver installer move to be under the component tree.
Added 'Enable Windows Long Path support' in 'after install' section
New Altera Self-Service Licensing Center

System-Level Debug & System Console

SignalTap Python API
o High-performing API using NumPy structured array
Interface-aware Node Finder
o High-performing API using NumPy structured array
Preserve for Debug support in Visual Designer Studio

Power & Thermal Analyzer

Improved Response Times
Asynchronous Power Calculations
TCL Script for EMIF IO placements
Improve formatting of generated reports
Support for asynchronous backend model
Integrated Heat Maps
GUI Enhancements including
o OPN selector ease-of-use enhancements
o Number alignment
o Disable PTA launch in Quartus for unsupported devices
o Enabling simplified “Find” support on reports
o Enhanced Edit View

Nios V & Embedded Software

Nios V: Standard C extension for compressed instruction support
Nios V/m: FreeRTOS driver support + pipelined ECC full support
Nios V example designs for Agilex 3 based Nios V Starter Kit
Agilex 5 HPS FreeRTOS – A76 and Symmetric Multi-Processing support
Yocto: support Mainline + Latest LTS
ATF: build-time choice of UART peripheral
OpenOCD support for Agilex 5 (D/E) and Agilex 3
App note on OpenOCD use for Agilex 5 / Agilex 3 HPS debug
HPS CPU benchmarks design example
GHRD/GSRD baseline updates + boot flows
Updated boot-flow support on Agilex 5 and Agilex 3 Devkits

In FPGA IP in Ver 26.1

Ethernet / Networking IP

TSN System Example Designs showcasing:
o 3 ETH-HIP Ethernet TSN MAC Hard IP (multi-port + dynamic reconfiguration)
o TSN 1G MRPHY IP static configuration
Agilex 5 System Example Designs highlighting:
o 10G and 25G Ethernet
o IEEE1588 PTP 10G and 25G
F-Tile Support features:
o AN/LT support for 2 new MR DR groups (4/8-lane)
o 10G soft MAC default mode for F-Tile 25G Ethernet Soft-IP
o FGT fractional PLL validation for Ethernet Hard IP

PCI Express / DMA / MCDMA

PCIe AXI MM Bridge for Root Port and End Point (MCDMA BAM/BAS) System Example Designs
o Agilex 3 / Agilex 5
o Small resource count
MCDMA PCIe Root Port system example (GHRD/GSRD) targeting Agilex 3 Dev Kit
Multi-IP system example: PCIe host attach to DDR w/ OFS

Radio /Fronthaul (eCPRI / CPRI / O-RAN / Interlaken / SerialLite)

Agilex 5 Hardware Example Designs
o CPRI MAC-SIP and PHY
o O-RAN IP and FrontHaul IP (10/25G)
o Interlaken MAC/PCS IP
o SerialLite IV MAC/PCS IP 28.1G duplex/simplex
eCPRI IP 50G IP showcasing
o 50G data rate
o Dynamic Reconfiguration 10G/25G with a compile-time option of 50G

Video & Display Connectivity

Multiple Agilex 5 Video IP Design Examples
o MIPI design examples for DSI and CSI
o HDMI 2.1 retransmit
o DisplayPort 2.0 (up to 20G)
o 12G SDI
Agilex 3 DevKit support in MIPI CSI/DSI example design

Downloads

Quartus Prime

Pro Edition

Advanced design flow, block-based design, interface planner, partial reconfiguration, and high-speed transceiver support

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Quartus Prime

Standard Edition

Broad legacy support, platform designer, partial reconfiguration, and core timing/power tools

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Quartus Prime

Lite Edition

Free access, essential design tools, basic compile flow, Signal Tap, and starter simulation

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Compare the Editions

Features

Platform Designer

Platform Designer is a system integration tool in the Quartus® Prime Software that automatically generates interconnect logic to connect intellectual property (IP) functions and subsystems, saving significant time and effort in the FPGA design process.

Details

Block-Based Design

Design, implement, and verify core or periphery blocks once, and then reuse those blocks multiple times across different projects that use the same device.

Details

Partial Reconfiguration

Reconfigure a portion of the FPGA dynamically while the remaining FPGA design continues to function.

Design Partition Planner

A design partition is a logical, named, hierarchical boundary that you can assign to an instance in your design. Defining a design partition allows you to optimize and lock down the compilation results for individual blocks.

Chip Planner

Chip Planner simplifies floorplanning by allowing you to view and constrain design logic within a visual display of the FPGA chip resources. You can use the Chip Planner to view and modify the logic placement, connections, and routing paths after running the Fitter.

Interface Planner

The Interface Planner explores a device’s peripheral architecture and efficiently assigns interfaces. The Interface Planner prevents illegal pin assignments by performing fitter and legality checks in real-time.

Logic Lock Regions

A Logic Lock region is a powerful type of logic placement and routing constraint. You can define any arbitrary region of physical resources on the target device as a Logic Lock region, and then assign design nodes and other properties to the region.

Multiprocessor Support (Faster Compile Time)

Using multi-processors for compilation can result in faster compile times depending on the number of cores used.

IP Base Suite

Altera provides full production licenses for some of its popular IP cores in the Altera FPGA IP Base Suite, which is free with the Quartus Prime Software and Quartus Prime Pro Edition Software.

Fitter (Place and Route)

The Compiler's Fitter performs design placement and routing. During place and route, the Fitter determines the best placement and routing of logic in the target FPGA device.

Register Retiming

Register Retiming can balance register chains by retiming (moving) ALM registers into Hyper-Registers in the routing fabric.

Timing Analyzer

The Timing Analyzer is a powerful ASIC-style timing analysis tool that validates the timing performance of all logic in your design using an industry-standard constraint, analysis, and reporting methodology.

Design Space Explorer II

The Design Space Explorer II tool allows you to find optimal project settings for resource, performance, or power optimization goals.

Power Analysis

Power analysis features include Early Power Estimators, Altera® FPGA Power and Thermal Calculator, and the Power Analyzer that give you the ability to estimate power consumption.

Signal Tap Logic Analyzer

The Signal Tap logic analyzer captures and displays the real-time signal behavior in an FPGA design allowing you to probe and debug the behavior of internal signals during normal device operation, without requiring extra I/O pins or external lab equipment.

Transceiver Toolkit

Transceiver Toolkit uses System Console technology to help FPGA and board designers validate transceiver link signal integrity in real-time in a system and improve board bring-up time.

Details

Questa*-FPGA Edition Software

Questa*-FPGA software editions are a version of the Siemens EDA Questa* Core software targeted for Altera® FPGAs devices.

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