What Is OpenCL?
The OpenCL standard is the first open, royalty-free, unified programming model for accelerating algorithms on heterogeneous systems. OpenCL allows the use of a C-based programming language for developing code across different platforms such as CPUs, GPUs, digital signal processors (DSP), and FPGAs.
OpenCL is a programming model for software engineers and a methodology for system architects. It is based on standard ANSI C (C99) with extensions to extract parallelism. OpenCL also includes an application program interface (API) for the host to communicate with the hardware accelerator, traditionally over PCI Express®, or one kernel to communicate with another without host interaction. In addition to this, Altera provides, as a vendor extension, an I/O Channel API to stream data into a kernel directly from a streaming I/O interface such as 10Gb Ethernet. A key benefit of OpenCL is that it is a portable open, royalty-free standard, which is a key differentiator versus proprietary programming models.
In the OpenCL model, the user schedules tasks to command queues, of which there is at least one for each device. The OpenCL run-time then breaks the data-parallel tasks into pieces and sends them to the processing elements in the device. This is the method for a host to communicate with any hardware accelerator. It is up to the individual hardware accelerator vendors to abstract away the vendor-specific implementation. The Altera SDK for OpenCL v14.0 does this and conforms to the OpenCL 1.0 standard.
For more information on the OpenCL 1.0 standard, refer to The OpenCL Specification (PDF) by Khronos.
OpenCL is supported by many vendors who are part of the Khronos group. For more information, visit http://www.khronos.org/opencl/
For an overview on OpenCL for Altera FPGAs, view the Accelerate Performance and Design Productivity with OpenCL on Altera FPGAs webcast.
What Is the Altera SDK for OpenCL?
The Altera SDK for OpenCL allows the easy implementation of applications onto FPGAs by abstracting away the complexities of FPGA design, allowing software programmers to write hardware-accelerated kernel functions in OpenCL C, an ANSI C-based language with additional OpenCL constructs. As part of our SDK we provide a suite of tools to further resemble the fast development flow of software programmers, including:
- An emulator to step through the code on an x86 and ensure it is functionally correct
- A detailed optimization report to understand the load and store inner loop dependencies
- A rapid prototyping tool to further push off the longer compile times associated with building an FPGA and run the kernel code on a prebuilt FPGA template
- A profiler that shows performance insight into the kernel to ensure proper memory coalescence and stall free hardware pipelines
- An OpenCL compiler capable of performing over 300 optimizations on the kernel code and producing the entire FPGA image in one step
The Altera SDK for OpenCL is in full production release, making Altera the first FPGA company to have a solution that conforms to the OpenCL specification. The Altera SDK for OpenCL supports a variety of host CPUs, including the embedded ARM® Cortex®-A9 processor cores in SoC devices, the IBM Power Series processors, and a standard x86 CPU. The Altera SDK for OpenCL supports scalable solutions on multiple FPGAs and multiple boards as well as a variety of memory targets, such as DDR SDRAM for sequential memory accesses, QDR SRAM for random memory accesses, or internal FPGA memory for low-latency memory access. Half-precision as well as single- and double-precision floating point is also supported.
For additional information on OpenCL: