Transceiver Toolkit

Real-Time Transceiver Access for Faster Board Bring Up

Transceiver Toolkit uses System Console technology to help FPGA and board designers validate transceiver link signal integrity real time in a system and improve board bring-up time. Test for bit-error rate (BER) while simultaneously running multiple links at your target data rate to validate your board design with Transceiver Toolkit. Tune transceiver analog settings for optimal link performance while using different test metrics to quantify results. Simultaneously test multiple devices across one or more boards using link tests in the Transceiver Toolkit GUI. Support for Intel® Stratix® 10 and Stratix V FPGAs and includes adaptive equalization (AEQ) and decision feedback equalization (DFE) for signal transmission robustness. The latest additions include support for Intel Stratix 10 GX 10 transceivers.

Transceiver Toolkit Features

  • Offers FPGA and board designers real-time access to transceiver settings and improve board bring-up time
  • Provides bit-error rate test (BERT) function with pseudo-random binary sequence (PRBS) pattern generator and checker
  • Includes channel manager interface to monitor and track status while testing multiple channels simultaneously
  • Runs link tests between multiple devices across one or more boards
  • Determines the width and height of the signal eye with Eye Viewer (available in selected devices)
  • Offers access to signal integrity hardware features including AEQ and DFE
  • Provides the AutoSweep feature with new interval-stepping capability that allows quick testing of many combinations of physical medium attachment (PMA) analog settings to find the optimal set for a particular transceiver link
  • Provides Eye Viewer integration with manual PMA setting controls and test plot management with save-and-load support that enables you to easily compare the signal integrity results
  • Provides new "AutoSweep & Eye Viewer" mode that allows automatic sweeping of PMA settings while capturing Eye Viewer data
  • Supports triggered adaptation mode DFE for Stratix V FPGAs and triggered and continuous DFE modes for Intel Stratix 10 FPGAs

Table 1. Transceiver Toolkit Device Support

  Device Family
Cyclone® V Arria® II GX Arria V GX / GT Arria V GZ Stratix IV GX / GT Stratix V GX Stratix V GT Intel Stratix 10 GX  Intel Arria 10 GX
Real-time access check check check check check check check check check
Built-in BERT function check check check check check check check check check
Multichannel test check check check check check check check check check
Mulitple devices link test check check check check check check check check check
Stratix FPGA Eye Viewer– signal eye width support - - - check check check check check -
Stratix FPGA Eye Viewer– signal eye height support - - - check - check check check -
AEQ - - - check - check - check check
DFE - - - check check check - check check