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Software and Tools
Altera High Level Synthesis Compiler
The High Level Synthesis (HLS) Compiler is discontinued. Migrate your existing designs to use "HLS IP Gen".
Overview
DISCONTINUED - The HLS Compiler is a high-level synthesis tool that converts untimed C++ code into optimized, production-quality RTL for Altera® FPGAs. By raising the abstraction level of design input, the HLS Compiler accelerates development and verification cycles compared to traditional RTL design flows. C++ models can typically be verified orders of magnitude faster, enabling more efficient iteration and system-level exploration.
The HLS Compiler is included with the Quartus® Prime Pro Edition software installation.
The High Level Synthesis (HLS) Compiler is discontinued. Migrate your existing designs to use HLS IP Gen.
Key Features
| ANSI C++ Design Entry | Uses untimed ANSI C++ as the golden design source |
| Architecture Exploration | Allows you to quickly explore multiple architectures through high-level directives |
| Constraint-Driven Design Simplification | Simplifies tool usage by inferring design intent from high-level constraints |
| IP Generation via Platform Designer | Generates reusable intellectual property (IP) for system integration using the Platform Designer |
| Interface Type Inference | Supports inference of streaming, memory mapped, or wire interfaces |
| Timing-Driven Scheduling and Mapping | Performs device-specific timing-driven schedule optimization and technology mapping for Altera FPGAs |
| Compiler Model and Standards Support | Supports a software compiler use model and industry standards including ac_int data types |
| Automated HTML Reporting | Detailed reporting feature for a birds-eye view: High-level design HTML reports are automatically generated during the simulation stage |
| Design Utilization Insights | Allows users to view and analyze: Area utilization, loop structure, memory usage, system data flow, clusters, and surrounding logic |
| Flexible IP Integration Flows | Supports multiple flows to integrate IP in a system. Integrate HLS code through direct HLD instantiation, through Platform Designer |
